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Searched refs:REG_INT_PMFIRE (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DhalMBXINT.c322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h148 #define REG_INT_PMFIRE 0x0000 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DhalMBXINT.c322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h148 #define REG_INT_PMFIRE 0x0000 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DhalMBXINT.c322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h148 #define REG_INT_PMFIRE 0x0000 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DhalMBXINT.c322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h148 #define REG_INT_PMFIRE 0x0000 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DhalMBXINT.c319 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
321 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
329 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
330 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h135 #define REG_INT_PMFIRE 0x0000 //51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DhalMBXINT.c318 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
319 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
327 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H2; in MHAL_MBXINT_Fire()
328 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H2); in MHAL_MBXINT_Fire()
H A DregMBXINT.h138 #define REG_INT_PMFIRE 0x0000 //PM51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DhalMBXINT.c321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
330 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DhalMBXINT.c321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h135 #define REG_INT_PMFIRE 0x0000 //51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DhalMBXINT.c318 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
319 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
327 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H2; in MHAL_MBXINT_Fire()
328 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H2); in MHAL_MBXINT_Fire()
H A DregMBXINT.h138 #define REG_INT_PMFIRE 0x0000 //PM51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DhalMBXINT.c321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h135 #define REG_INT_PMFIRE 0x0000 //51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DhalMBXINT.c374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DhalMBXINT.c374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h160 #define REG_INT_PMFIRE 0x0000 //51 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DhalMBXINT.c374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DhalMBXINT.c374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DhalMBXINT.c374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()

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