1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 ///////////////////////////////////////////////////////////////////////////////////////////////////
95 ///
96 /// file halMBXINT.c
97 /// @brief MStar MailBox interrupt DDI
98 /// @author MStar Semiconductor Inc.
99 ///////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #define _MHAL_MBX_INTERRUPT_C
102
103 //=============================================================================
104 // Include Files
105 //=============================================================================
106 #include "MsCommon.h"
107 #include "drvMBX.h"
108 #include "regMBXINT.h"
109 #include "halMBXINT.h"
110
111 //=============================================================================
112 // Compile options
113 //=============================================================================
114
115
116 //=============================================================================
117 // Local Defines
118 //=============================================================================
119
120 //=============================================================================
121 // Debug Macros
122 //=============================================================================
123 //#define MBXINT_DEBUG
124 #ifdef MBXINT_DEBUG
125 #define MBXINT_ERROR(fmt, args...) printf("[MBX INT Driver USER ERR][%06d] " fmt, __LINE__, ## args)
126 #define MBXINT_WARN(fmt, args...) printf("[MBX INT Driver WARN][%06d] " fmt, __LINE__, ## args)
127 #define MBXINT_PRINT(fmt, args...) printf("[MBX INT Driver][%06d] " fmt, __LINE__, ## args)
128 #define MBXINT_ASSERT(_cnd, _fmt, _args...) \
129 if (!(_cnd)) { \
130 MBXINT_PRINT(_fmt, ##_args); \
131 }
132 #else
133 #define MBXINT_ERROR(fmt, args...)
134 #define MBXINT_WARN(fmt, args...)
135 #define MBXINT_PRINT(fmt, args...)
136 #define MBXINT_ASSERT(_cnd, _fmt, _args...)
137 #endif
138
139 //=============================================================================
140 // Macros
141 //=============================================================================
142
143 //=============================================================================
144 // Local Variables
145 //=============================================================================
146 static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
147 static MS_VIRT _virtRIUBaseAddrMBXINT = 0;
148
149 //=============================================================================
150 // Global Variables
151 //=============================================================================
152
153 //=============================================================================
154 // Local Function Prototypes
155 //=============================================================================
156 static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
157 static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);
158
159 //=============================================================================
160 // Local Function
161 //=============================================================================
162
163 //-------------------------------------------------------------------------------------------------
164 /// Handle Interrupt, schedule tasklet
165 /// @param irq \b IN: interrupt number
166 /// @param dev_id \b IN: dev id
167 /// @return irqreturn_t: IRQ_HANDLED
168 /// @attention
169 /// <b>[MXLIB] <em></em></b>
170 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_INTHandler(InterruptNum eIntNum)171 void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
172 {
173 if(NULL == _pMBXMsgRecvCbFunc)
174 {
175 return;
176 }
177
178 _pMBXMsgRecvCbFunc(eIntNum);
179
180 MsOS_EnableInterrupt(eIntNum);
181 }
182
183 //-------------------------------------------------------------------------------------------------
184 /// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
185 /// @param eHostCPUID \b IN: The Host CPU ID
186 /// @return E_MBX_SUCCESS
187 /// @attention
188 /// <b>[MXLIB] <em></em></b>
189 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)190 MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
191 {
192 switch(eHostCPUID)
193 {
194 case E_MBX_CPU_PM:
195 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
196 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
197 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
198 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_8051);
199 break;
200 case E_MBX_CPU_AEON:
201 //MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
202 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
203 //MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
204 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
205 break;
206 case E_MBX_CPU_MIPS:
207 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
208 //MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
209 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
210 //MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
211 break;
212 default:
213 return E_MBX_ERR_INVALID_CPU_ID;
214 }
215
216 return E_MBX_SUCCESS;
217 }
218
219 //=============================================================================
220 // Mailbox HAL Interrupt Driver Function
221 //=============================================================================
222
223 //-------------------------------------------------------------------------------------------------
224 /// Handle Interrupt INIT
225 /// @param eHostCPU \b IN: interrupt owner
226 /// @param pMBXRecvMsgCBFunc \b IN: callback func by driver
227 /// @param u32RIUBaseAddrMBXINT \b IN: RIU Base Addr with platform
228 /// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
229 /// @return E_MBX_UNKNOW_ERROR: request_irq failed;
230 /// @return E_MBX_SUCCESS: success;
231 /// @attention
232 /// <b>[MXLIB] <em></em></b>
233 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Init(MBX_CPU_ID eHostCPU,MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc,MS_VIRT virtRIUBaseAddrMBXINT)234 MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_VIRT virtRIUBaseAddrMBXINT)
235 {
236 _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
237 _virtRIUBaseAddrMBXINT = virtRIUBaseAddrMBXINT;
238
239 return _MHAL_MBXINT_SetHostCPU(eHostCPU);
240 }
241
242 //-------------------------------------------------------------------------------------------------
243 /// Handle Interrupt DeINIT
244 /// @param eHostCPU \b IN: interrupt owner
245 /// @return void;
246 /// @attention
247 /// <b>[MXLIB] <em></em></b>
248 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_DeInit(MBX_CPU_ID eHostCPU)249 void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
250 {
251 switch(eHostCPU)
252 {
253 case E_MBX_CPU_PM:
254 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
255 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_8051);
256 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
257 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_8051);
258 break;
259 case E_MBX_CPU_AEON:
260 //MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
261 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_AEON);
262 //MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
263 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_AEON);
264 break;
265 case E_MBX_CPU_MIPS:
266 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
267 //MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_BEON);
268 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
269 //MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_BEON);
270 break;
271 default:
272 break;
273 }
274 }
275
276 //-------------------------------------------------------------------------------------------------
277 /// Reset Host CPU for MBX Interrupt
278 /// @param ePrevCPU \b IN: previous host cpu id
279 /// @param eConfigCpu \b IN: new configed cpu id
280 /// @return E_MBX_SUCCESS: success;
281 /// @return E_MBX_INVALID_CPU_ID
282 /// @attention
283 /// <b>[MXLIB] <em></em></b>
284 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_ResetHostCPU(MBX_CPU_ID ePrevCPU,MBX_CPU_ID eConfigCpu)285 MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
286 {
287 MHAL_MBXINT_DeInit(ePrevCPU);
288
289 return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
290 }
291
292 //-------------------------------------------------------------------------------------------------
293 /// Fire Interrupt
294 /// @param dstCPUID \b IN: dst cpu of interrupt
295 /// @param srcCPUID \b IN: src cpu of interrupt
296 /// @return E_MBX_SUCCESS: success;
297 /// @attention
298 /// <b>[MXLIB] <em></em></b>
299 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Fire(MBX_CPU_ID dstCPUID,MBX_CPU_ID srcCPUID)300 MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
301 {
302 MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
303
304 #if defined(MSOS_TYPE_NUTTX)
305 srcCPUID = E_MBX_CPU_AEON;
306 dstCPUID = E_MBX_CPU_MIPS;
307
308
309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2;
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2;
311
312 return E_MBX_SUCCESS;
313
314 #endif
315
316 switch(srcCPUID)
317 {
318 case E_MBX_CPU_PM:
319 if(dstCPUID==E_MBX_CPU_AEON)
320 {
321 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
323 //MBXINT_PRINT("[RIU ADDR] = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
325 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
326 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
327 }
328 else
329 { // PM 2 MIPS
330 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H3);
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3;
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3);
333 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
334 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
335 }
336
337 break;
338 case E_MBX_CPU_AEON:
339 if(dstCPUID==E_MBX_CPU_PM)
340 {
341 // AEON 2 PM
342 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
345 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
346 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
347 }
348 else
349 {
350 // AEON 2 MIPS
351 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H3);
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3;
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3);
354 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
355 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
356 }
357
358 break;
359 case E_MBX_CPU_MIPS:
360 if(dstCPUID==E_MBX_CPU_PM)
361 {
362 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_PM);
363 CPU_INT_REG(REG_INT_H2FIRE) |= INT_H2_PM;
364 CPU_INT_REG(REG_INT_H2FIRE) &= ~(INT_H2_PM);
365 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
366 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
367 }
368 else
369 {
370 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_AEON);
371 CPU_INT_REG(REG_INT_H3FIRE) |= INT_H3_AEON;
372 CPU_INT_REG(REG_INT_H3FIRE) &= ~(INT_H3_AEON);
373 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
374 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
375 }
376
377 break;
378 default:
379 MBXINT_ASSERT(FALSE,"wrong src cpu!\n");
380 break;
381 }
382
383 return E_MBX_SUCCESS;
384 }
385
MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)386 MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
387 {
388 if((eHKCPU == E_MBX_CPU_AEON) || (eHKCPU == E_MBX_CPU_MIPS) ||
389 (eHKCPU == E_MBX_CPU_MIPS_VPE1))
390 {
391 return E_MBX_SUCCESS;
392 }
393 MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");
394 return E_MBX_ERR_INVALID_CPU_ID;
395 }
396