xref: /utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/regMBXINT.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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//<MStar Software>

#ifndef _MHAL_MBX_INTERRUPT_REG_H
#define _MHAL_MBX_INTERRUPT_REG_H

//=============================================================================
// Includs
//=============================================================================

//=============================================================================
// Defines & Macros
//=============================================================================
#define RIU_MAP _u32RIUBaseAddrMBXINT

#define RIU     ((unsigned short volatile *) RIU_MAP)
#define RIU8    ((unsigned char  volatile *) RIU_MAP)

//#############################
//# host0: 51               (bank : 1019h)
//# host1: Secure R2        (bank : 1211h)
//# host2: ARM CA9 Core0    (bank : 1019h)
//# host3: ARM CA9 Core1    (bank : 1019h)
//#############################
#define REG_FIQ_MASK_BASE               (0xC80<<1)
#define FIQ_REG(address)                RIU[address*2+REG_FIQ_MASK_BASE]

#define REG_FIQ_H1_48_63                0x0047 //mask
#if 0
    // host3 to x
    #define INT_FIQMASK_H3_H2           BIT(0)
    #define INT_FIQMASK_H3_AEON         BIT(1)
    #define INT_FIQMASK_H3_PM           BIT(2)
#endif

#define REG_FIQ_H1_32_47                0x0046 //mask
    // host0 to x
    #define INT_FIQMASK_PM_H3           BIT(4)
    #define INT_FIQMASK_PM_H2           BIT(5)
    #define INT_FIQMASK_PM_AEON         BIT(6)
    // host1 to x
    #define INT_FIQMASK_AEON_H3         BIT(8)
    #define INT_FIQMASK_AEON_H2         BIT(9)
    #define INT_FIQMASK_AEON_PM         BIT(10)

    // host2 to x
    #define INT_FIQMASK_H2_H3           BIT(12)
    #define INT_FIQMASK_H2_AEON         BIT(13)
    #define INT_FIQMASK_H2_PM           BIT(14)

#define REG_FIQS_H1_32_47               0x004e //status
#define REG_FIQS_H1_48_63               0x004f //status


//#############################
//# host0: 51                       (bank : 1019h)
//# host1: ARM CA7 Core0    (bank : 1019h)
//# host2: Secure R2            (bank : 1211h)
//# host3: ARM CA7 Core1    (bank : 1019h)
//#############################
#define REG_CPU_INT_BASE                (0x2A0<<1)
#define CPU_INT_REG(address)            RIU[address*2+REG_CPU_INT_BASE]
#define REG_INT_PMFIRE                  0x0000 //PM51
    #define INT_PM_AEON                 BIT(1)
    #define INT_PM_H2                   BIT(0)
    #define INT_PM_H3                   BIT(2)

#define REG_INT_AEONFIRE                0x0002 //R2
    #define INT_AEON_PM                 BIT(0)
    #define INT_AEON_H2                 BIT(1)
    #define INT_AEON_H3                 BIT(2)

#define REG_INT_H2FIRE                  0x0004 //ARM CA7 Core 0
    #define INT_H2_PM                   BIT(0)
    #define INT_H2_AEON                 BIT(1)
    #define INT_H2_H3                   BIT(2)

#define REG_INT_H3FIRE                  0x0006 //ARM CA7 Core 1
    #define INT_H3_PM                   BIT(0)
    #define INT_H3_AEON                 BIT(1)
    #define INT_H3_H2                   BIT(2)

#endif //_MHAL_MBX_INTERRUPT_REG_H