1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _MHAL_MBX_INTERRUPT_REG_H 80 #define _MHAL_MBX_INTERRUPT_REG_H 81 82 //============================================================================= 83 // Includs 84 //============================================================================= 85 86 //============================================================================= 87 // Defines & Macros 88 //============================================================================= 89 #define RIU_MAP _u32RIUBaseAddrMBXINT 90 91 #define RIU ((unsigned short volatile *) RIU_MAP) 92 #define RIU8 ((unsigned char volatile *) RIU_MAP) 93 94 //############################# 95 //# host0: 51 (bank : 1019h) 96 //# host1: Secure R2 (bank : 1211h) 97 //# host2: ARM CA9 Core0 (bank : 1019h) 98 //# host3: ARM CA9 Core1 (bank : 1019h) 99 //############################# 100 #define REG_FIQ_MASK_BASE (0xC80<<1) 101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] 102 103 #define REG_FIQ_H1_48_63 0x0047 //mask 104 #if 0 105 // host3 to x 106 #define INT_FIQMASK_H3_H2 BIT(0) 107 #define INT_FIQMASK_H3_AEON BIT(1) 108 #define INT_FIQMASK_H3_PM BIT(2) 109 #endif 110 111 #define REG_FIQ_H1_32_47 0x0046 //mask 112 // host0 to x 113 #define INT_FIQMASK_PM_H3 BIT(4) 114 #define INT_FIQMASK_PM_H2 BIT(5) 115 #define INT_FIQMASK_PM_AEON BIT(6) 116 // host1 to x 117 #define INT_FIQMASK_AEON_H3 BIT(8) 118 #define INT_FIQMASK_AEON_H2 BIT(9) 119 #define INT_FIQMASK_AEON_PM BIT(10) 120 121 // host2 to x 122 #define INT_FIQMASK_H2_H3 BIT(12) 123 #define INT_FIQMASK_H2_AEON BIT(13) 124 #define INT_FIQMASK_H2_PM BIT(14) 125 126 #define REG_FIQS_H1_32_47 0x004e //status 127 #define REG_FIQS_H1_48_63 0x004f //status 128 129 130 //############################# 131 //# host0: 51 (bank : 1019h) 132 //# host1: ARM CA7 Core0 (bank : 1019h) 133 //# host2: Secure R2 (bank : 1211h) 134 //# host3: ARM CA7 Core1 (bank : 1019h) 135 //############################# 136 #define REG_CPU_INT_BASE (0x2A0<<1) 137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] 138 #define REG_INT_PMFIRE 0x0000 //PM51 139 #define INT_PM_AEON BIT(1) 140 #define INT_PM_H2 BIT(0) 141 #define INT_PM_H3 BIT(2) 142 143 #define REG_INT_AEONFIRE 0x0002 //R2 144 #define INT_AEON_PM BIT(0) 145 #define INT_AEON_H2 BIT(1) 146 #define INT_AEON_H3 BIT(2) 147 148 #define REG_INT_H2FIRE 0x0004 //ARM CA7 Core 0 149 #define INT_H2_PM BIT(0) 150 #define INT_H2_AEON BIT(1) 151 #define INT_H2_H3 BIT(2) 152 153 #define REG_INT_H3FIRE 0x0006 //ARM CA7 Core 1 154 #define INT_H3_PM BIT(0) 155 #define INT_H3_AEON BIT(1) 156 #define INT_H3_H2 BIT(2) 157 158 #endif //_MHAL_MBX_INTERRUPT_REG_H 159 160 161