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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 ///////////////////////////////////////////////////////////////////////////////////////////////////
95 ///
96 /// file halMBXINT.c
97 /// @brief MStar MailBox interrupt DDI
98 /// @author MStar Semiconductor Inc.
99 ///////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #define _MHAL_MBX_INTERRUPT_C
102
103 //=============================================================================
104 // Include Files
105 //=============================================================================
106 #include "MsCommon.h"
107 #include "drvMBX.h"
108 #include "regMBXINT.h"
109 #include "halMBXINT.h"
110
111 //=============================================================================
112 // Compile options
113 //=============================================================================
114
115
116 //=============================================================================
117 // Local Defines
118 //=============================================================================
119
120 //=============================================================================
121 // Debug Macros
122 //=============================================================================
123 //#define MBXINT_DEBUG
124 #ifdef MBXINT_DEBUG
125 #define MBXINT_ERROR(fmt, args...) printf("[MBX INT Driver USER ERR][%06d] " fmt, __LINE__, ## args)
126 #define MBXINT_WARN(fmt, args...) printf("[MBX INT Driver WARN][%06d] " fmt, __LINE__, ## args)
127 #define MBXINT_PRINT(fmt, args...) printf("[MBX INT Driver][%06d] " fmt, __LINE__, ## args)
128 #define MBXINT_ASSERT(_cnd, _fmt, _args...) \
129 if (!(_cnd)) { \
130 MBXINT_PRINT(_fmt, ##_args); \
131 }
132 #else
133 #define MBXINT_ERROR(fmt, args...)
134 #define MBXINT_WARN(fmt, args...)
135 #define MBXINT_PRINT(fmt, args...)
136 #define MBXINT_ASSERT(_cnd, _fmt, _args...)
137 #endif
138
139 //=============================================================================
140 // Macros
141 //=============================================================================
142
143 //=============================================================================
144 // Local Variables
145 //=============================================================================
146 static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
147 static MS_VIRT _virtRIUBaseAddrMBXINT = 0;
148
149 //=============================================================================
150 // Global Variables
151 //=============================================================================
152
153 //=============================================================================
154 // Local Function Prototypes
155 //=============================================================================
156 static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
157 static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);
158
159 //=============================================================================
160 // Local Function
161 //=============================================================================
162
163 //-------------------------------------------------------------------------------------------------
164 /// Handle Interrupt, schedule tasklet
165 /// @param irq \b IN: interrupt number
166 /// @param dev_id \b IN: dev id
167 /// @return irqreturn_t: IRQ_HANDLED
168 /// @attention
169 /// <b>[MXLIB] <em></em></b>
170 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_INTHandler(InterruptNum eIntNum)171 void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
172 {
173 if(NULL == _pMBXMsgRecvCbFunc)
174 {
175 return;
176 }
177
178 _pMBXMsgRecvCbFunc(eIntNum);
179
180 MsOS_EnableInterrupt(eIntNum);
181 }
182
183 //-------------------------------------------------------------------------------------------------
184 /// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
185 /// @param eHostCPUID \b IN: The Host CPU ID
186 /// @return E_MBX_SUCCESS
187 /// @attention
188 /// <b>[MXLIB] <em></em></b>
189 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)190 MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
191 {
192 switch(eHostCPUID)
193 {
194 case E_MBX_CPU_PM:
195 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
196 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
197 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
198 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_8051);
199 break;
200 case E_MBX_CPU_AEON:
201 //MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
202 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
203 //MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
204 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
205 break;
206 case E_MBX_CPU_MIPS:
207 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
208 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
209
210 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_BEON);
211 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
212 break;
213
214 default:
215 return E_MBX_ERR_INVALID_CPU_ID;
216 }
217 return E_MBX_SUCCESS;
218 }
219
220 //=============================================================================
221 // Mailbox HAL Interrupt Driver Function
222 //=============================================================================
223
224 //-------------------------------------------------------------------------------------------------
225 /// Handle Interrupt INIT
226 /// @param eHostCPU \b IN: interrupt owner
227 /// @param pMBXRecvMsgCBFunc \b IN: callback func by driver
228 /// @param u32RIUBaseAddrMBXINT \b IN: RIU Base Addr with platform
229 /// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
230 /// @return E_MBX_UNKNOW_ERROR: request_irq failed;
231 /// @return E_MBX_SUCCESS: success;
232 /// @attention
233 /// <b>[MXLIB] <em></em></b>
234 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Init(MBX_CPU_ID eHostCPU,MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc,MS_VIRT virtRIUBaseAddrMBXINT)235 MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_VIRT virtRIUBaseAddrMBXINT)
236 {
237 _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
238 _virtRIUBaseAddrMBXINT = virtRIUBaseAddrMBXINT;
239
240 return _MHAL_MBXINT_SetHostCPU(eHostCPU);
241 }
242
243 //-------------------------------------------------------------------------------------------------
244 /// Handle Interrupt DeINIT
245 /// @param eHostCPU \b IN: interrupt owner
246 /// @return void;
247 /// @attention
248 /// <b>[MXLIB] <em></em></b>
249 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_DeInit(MBX_CPU_ID eHostCPU)250 void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
251 {
252 switch(eHostCPU)
253 {
254 case E_MBX_CPU_PM:
255 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
256 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_8051);
257 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
258 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_8051);
259 break;
260 case E_MBX_CPU_AEON:
261 //MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
262 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_AEON);
263 //MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
264 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_AEON);
265 break;
266 case E_MBX_CPU_MIPS:
267 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_BEON);
268 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_BEON);
269 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_BEON);
270 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_BEON);
271 break;
272 default:
273 break;
274 }
275 }
276
277 //-------------------------------------------------------------------------------------------------
278 /// Reset Host CPU for MBX Interrupt
279 /// @param ePrevCPU \b IN: previous host cpu id
280 /// @param eConfigCpu \b IN: new configed cpu id
281 /// @return E_MBX_SUCCESS: success;
282 /// @return E_MBX_INVALID_CPU_ID
283 /// @attention
284 /// <b>[MXLIB] <em></em></b>
285 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_ResetHostCPU(MBX_CPU_ID ePrevCPU,MBX_CPU_ID eConfigCpu)286 MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
287 {
288 MHAL_MBXINT_DeInit(ePrevCPU);
289
290 return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
291 }
292
293 //-------------------------------------------------------------------------------------------------
294 /// Fire Interrupt
295 /// @param dstCPUID \b IN: dst cpu of interrupt
296 /// @param srcCPUID \b IN: src cpu of interrupt
297 /// @return E_MBX_SUCCESS: success;
298 /// @attention
299 /// <b>[MXLIB] <em></em></b>
300 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Fire(MBX_CPU_ID dstCPUID,MBX_CPU_ID srcCPUID)301 MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
302 {
303 MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
304
305 #if defined(MSOS_TYPE_NUTTX)
306 srcCPUID = E_MBX_CPU_AEON;
307 dstCPUID = E_MBX_CPU_MIPS;
308
309
310 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
311 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1;
312 return E_MBX_SUCCESS;
313 #endif
314
315 switch(srcCPUID)
316 {
317 case E_MBX_CPU_PM:
318 if(dstCPUID==E_MBX_CPU_AEON)
319 {
320 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
322 //MBXINT_PRINT("[RIU ADDR] = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
324 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
325 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
326 }
327 else
328 { // PM 2 MIPS
329 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H3);
330 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1;
331 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1);
332 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
333 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
334 }
335
336 break;
337 case E_MBX_CPU_AEON:
338 if(dstCPUID==E_MBX_CPU_PM)
339 {
340 // AEON 2 PM
341 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
344 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
345 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
346 }
347 else
348 {
349 // AEON 2 MIPS
350 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H3);
351 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
352 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1);
353 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
354 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
355 }
356
357 break;
358 case E_MBX_CPU_MIPS:
359 if(dstCPUID==E_MBX_CPU_PM)
360 {
361 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_PM);
362 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_PM;
363 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_PM);
364 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
365 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
366 }
367 else if(dstCPUID==E_MBX_CPU_AEON)
368 {
369 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_AEON);
370 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_AEON;
371 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_AEON);
372 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
373 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
374 }
375 #if 1//frcr2_integration###
376 else if(dstCPUID==E_MBX_CPU_R2FRC)
377 {
378 FRC_CPU_INT_REG(REG_FRCINT_HKCPUFIRE) |= INT_HKCPU_FRCR2;
379 FRC_CPU_INT_REG(REG_FRCINT_HKCPUFIRE) &= ~(INT_HKCPU_FRCR2);
380 MBXINT_PRINT("FIA [0-15]M = 0x%x\n", FIQ_FRCREG(REG_FRCFIQ_H1_0_15));
381 MBXINT_PRINT("FIQ [0-15]S = 0x%x\n", FIQ_FRCREG(REG_FRCFIQS_H1_0_15));
382 }
383 #endif
384
385 break;
386 default:
387 MBXINT_ASSERT(FALSE,"wrong src cpu!\n");
388 break;
389 }
390
391 return E_MBX_SUCCESS;
392 }
393
MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)394 MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
395 {
396 if((eHKCPU == E_MBX_CPU_AEON) || \
397 (eHKCPU == E_MBX_CPU_MIPS) || \
398 (eHKCPU == E_MBX_CPU_MIPS_VPE1))
399 {
400 return E_MBX_SUCCESS;
401 }
402 MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");
403 return E_MBX_ERR_INVALID_CPU_ID;
404 }
405