xref: /utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/halMBXINT.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

//<MStar Software>
//******************************************************************************
// MStar Software
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//<MStar Software>

#define _MHAL_MBX_INTERRUPT_C

//=============================================================================
// Include Files
//=============================================================================
#include "MsCommon.h"
#include "drvMBX.h"
#include "regMBXINT.h"
#include "halMBXINT.h"
#include "ULog.h"

//=============================================================================
// Compile options
//=============================================================================

//=============================================================================
// Local Defines
//=============================================================================
#define TAG_MBX "MBX"

//=============================================================================
// Debug Macros
//=============================================================================
//#define MBXINT_DEBUG
#ifdef MBXINT_DEBUG
    #define MBXINT_ERROR(fmt, args...)           ULOGE(TAG_MBX, "[MBX INT Driver USER ERR][%06d]     " fmt, __LINE__, ## args)
    #define MBXINT_WARN(fmt, args...)            ULOGW(TAG_MBX, "[MBX INT Driver WARN][%06d]    " fmt, __LINE__, ## args)
    #define MBXINT_PRINT(fmt, args...)           ULOGD(TAG_MBX, "[MBX INT Driver][%06d]     " fmt, __LINE__, ## args)
    #define MBXINT_ASSERT(_cnd, _fmt, _args...)    \
                                    if (!(_cnd)) {  \
                                        MBXINT_PRINT(_fmt, ##_args);  \
                                    }
#else
    #define MBXINT_ERROR(fmt, args...)
    #define MBXINT_WARN(fmt, args...)
    #define MBXINT_PRINT(fmt, args...)
    #define MBXINT_ASSERT(_cnd, _fmt, _args...)
#endif

//=============================================================================
// Macros
//=============================================================================

//=============================================================================
// Local Variables
//=============================================================================
static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
static MS_VIRT _virtRIUBaseAddrMBXINT = 0;

//=============================================================================
// Global Variables
//=============================================================================

//=============================================================================
// Local Function Prototypes
//=============================================================================
static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);

//=============================================================================
// Local Function
//=============================================================================

//-------------------------------------------------------------------------------------------------
/// Handle Interrupt, schedule tasklet
/// @param  irq                  \b IN: interrupt number
/// @param  dev_id                  \b IN: dev id
/// @return irqreturn_t: IRQ_HANDLED
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
{
    if(NULL == _pMBXMsgRecvCbFunc)
    {
        return;
    }

    _pMBXMsgRecvCbFunc(eIntNum);

    MsOS_EnableInterrupt(eIntNum);
}

//-------------------------------------------------------------------------------------------------
/// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
/// @param  eHostCPUID                  \b IN: The Host CPU ID
/// @return E_MBX_SUCCESS
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
{
    switch(eHostCPUID)
    {
        case E_MBX_CPU_PM:
        {
            MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
            MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_8051);
        }
        break;

        case E_MBX_CPU_AEON:
        {
            MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
            MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
        }
        break;

        case E_MBX_CPU_MIPS:
        {
            MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
            MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_BEON);
            MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
        }
        break;

        default:
            return E_MBX_ERR_INVALID_CPU_ID;
    }

    return E_MBX_SUCCESS;
}

//=============================================================================
// Mailbox HAL Interrupt Driver Function
//=============================================================================

//-------------------------------------------------------------------------------------------------
/// Handle Interrupt INIT
/// @param  eHostCPU                  \b IN: interrupt owner
/// @param  pMBXRecvMsgCBFunc                  \b IN: callback func by driver
/// @param  u32RIUBaseAddrMBXINT                  \b IN: RIU Base Addr with platform
/// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
/// @return E_MBX_UNKNOW_ERROR: request_irq failed;
/// @return E_MBX_SUCCESS: success;
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_VIRT virtRIUBaseAddrMBXINT)
{
    _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
    _virtRIUBaseAddrMBXINT = virtRIUBaseAddrMBXINT;

    return _MHAL_MBXINT_SetHostCPU(eHostCPU);
}

//-------------------------------------------------------------------------------------------------
/// Handle Interrupt DeINIT
/// @param  eHostCPU                  \b IN: interrupt owner
/// @return void;
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
{
    switch(eHostCPU)
    {
        case E_MBX_CPU_PM:
        {
            MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
            MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_8051);
            MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
            MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_8051);
        }
        break;

        case E_MBX_CPU_AEON:
        {
            MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
            MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_AEON);
            MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
            MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_AEON);
        }
        break;

        case E_MBX_CPU_MIPS:
        {
            MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_BEON);
            MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_BEON);
            MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_BEON);
            MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_BEON);
        }
        break;

        default:
            break;
    }
}

//-------------------------------------------------------------------------------------------------
/// Reset Host CPU for MBX Interrupt
/// @param  ePrevCPU                  \b IN: previous host cpu id
/// @param  eConfigCpu                  \b IN: new configed cpu id
/// @return E_MBX_SUCCESS: success;
/// @return E_MBX_INVALID_CPU_ID
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
{
    MHAL_MBXINT_DeInit(ePrevCPU);

    return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
}

//-------------------------------------------------------------------------------------------------
/// Fire Interrupt
/// @param  dstCPUID                  \b IN: dst cpu of interrupt
/// @param  srcCPUID                  \b IN: src cpu of interrupt
/// @return E_MBX_SUCCESS: success;
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
{
    MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");

#if defined(MSOS_TYPE_NUTTX)
    srcCPUID = E_MBX_CPU_AEON;
    dstCPUID = E_MBX_CPU_MIPS;


    CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
    CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1;

    return  E_MBX_SUCCESS;

#endif

    switch(srcCPUID)
    {
        case E_MBX_CPU_PM:
        {
            if(dstCPUID==E_MBX_CPU_AEON)
            {
                //PM51-to-R2
                //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
                CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
                //MBXINT_PRINT("[RIU ADDR] = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
                CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
                MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
                MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
            }
            else
            {
                //PM51-to-ARM Core 0
                //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H3);
                CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1;
                CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1);
                MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
                MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
            }
        }
        break;

        case E_MBX_CPU_AEON:
        {
            if(dstCPUID==E_MBX_CPU_PM)
            {
                //R2-to-PM51
                //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
                CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
                CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
                MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
                MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
            }
            else
            {
                //R2-to-ARM Core 0
                //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H3);
                CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
                CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1);
                MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
                MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
            }
        }
        break;

        case E_MBX_CPU_MIPS:
        {
            if(dstCPUID==E_MBX_CPU_PM)
            {
                //ARM Core 0-to-PM51
                //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_PM);
                CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_PM;
                CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_PM);
                MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
                MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
            }
            else
            {
                //ARM Core 0-to-R2
                //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_AEON);
                CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_AEON;
                CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_AEON);
                MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
                MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
            }
        }
        break;

        default:
        {
            MBXINT_ASSERT(FALSE, "wrong src cpu!\n");
        }
        break;
    }

    return E_MBX_SUCCESS;
}

MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
{
    if((eHKCPU == E_MBX_CPU_AEON) || \
       (eHKCPU == E_MBX_CPU_MIPS) || \
       (eHKCPU == E_MBX_CPU_MIPS_VPE1))
    {
        return E_MBX_SUCCESS;
    }

    MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");

    return E_MBX_ERR_INVALID_CPU_ID;
}