Home
last modified time | relevance | path

Searched refs:REG_CLKGEN2_STC3_CW_EN (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DhalTSP.c2322 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_STC_Init()
2323 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_STC_Init()
2324 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_STC_Init()
2456 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_SetSTCSynth()
2457 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
2458 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_SetSTCSynth()
H A DregTSP.h231 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c3974 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_STC_Init()
3975 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_STC_Init()
3976 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_STC_Init()
4076 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_SetSTCSynth()
4077 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
4078 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN); in HAL_TSP_SetSTCSynth()
H A DregTSP.h170 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c312 #define REG_CLKGEN2_STC3_CW_EN 0x0400UL macro
3682 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3683 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3684 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c312 #define REG_CLKGEN2_STC3_CW_EN 0x0400UL macro
3665 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3666 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3667 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c320 #define REG_CLKGEN2_STC3_CW_EN 0x0400UL macro
3761 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3762 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3763 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c320 #define REG_CLKGEN2_STC3_CW_EN 0x0400UL macro
3722 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3723 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3724 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h170 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h171 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h171 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h171 #define REG_CLKGEN2_STC3_CW_EN 0x0400 macro