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Searched refs:REG_CLKGEN2_STC2_CW_SEL (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h228 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro
H A DhalTSP.c2286 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_STC_Init()
2436 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c309 #define REG_CLKGEN2_STC2_CW_SEL 0x0002UL macro
3670 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3676 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c309 #define REG_CLKGEN2_STC2_CW_SEL 0x0002UL macro
3653 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3659 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c317 #define REG_CLKGEN2_STC2_CW_SEL 0x0002UL macro
3749 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3755 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c317 #define REG_CLKGEN2_STC2_CW_SEL 0x0002UL macro
3710 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3716 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h167 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h168 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h168 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h167 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro
H A DhalTSP.c3950 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_STC_Init()
4056 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h168 #define REG_CLKGEN2_STC2_CW_SEL 0x0002 macro