Searched refs:REG_CLKGEN2_DC0_STC3_CW_L (Results 1 – 12 of 12) sorted by relevance
235 #define REG_CLKGEN2_DC0_STC3_CW_L 0x4D macro
2301 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = 0x0000; in HAL_TSP_STC_Init()2378 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L); in HAL_TSP_GetSTCSynth()2452 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
315 #define REG_CLKGEN2_DC0_STC3_CW_L 0x33UL macro3631 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()3680 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
315 #define REG_CLKGEN2_DC0_STC3_CW_L 0x33UL macro3614 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()3663 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
323 #define REG_CLKGEN2_DC0_STC3_CW_L 0x33UL macro3710 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()3759 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
323 #define REG_CLKGEN2_DC0_STC3_CW_L 0x33UL macro3671 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()3720 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
174 #define REG_CLKGEN2_DC0_STC3_CW_L 0x4D macro
175 #define REG_CLKGEN2_DC0_STC3_CW_L 0x4D macro
3961 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = 0x0000; in HAL_TSP_STC_Init()4018 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L); in HAL_TSP_GetSTCSynth()4072 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()