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Searched refs:REG_CLKGEN2_DC0_STC3_CW_H (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h236 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro
H A DhalTSP.c2302 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = 0x2800; in HAL_TSP_STC_Init()
2379 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
2453 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c316 #define REG_CLKGEN2_DC0_STC3_CW_H 0x34UL macro
3631 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()
3681 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c316 #define REG_CLKGEN2_DC0_STC3_CW_H 0x34UL macro
3614 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()
3664 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c324 #define REG_CLKGEN2_DC0_STC3_CW_H 0x34UL macro
3710 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()
3760 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c324 #define REG_CLKGEN2_DC0_STC3_CW_H 0x34UL macro
3671 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H)); in HAL_TSP_GetSTCSynth()
3721 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h175 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h176 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h176 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h175 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro
H A DhalTSP.c3962 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = 0x2800; in HAL_TSP_STC_Init()
4019 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
4073 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h176 #define REG_CLKGEN2_DC0_STC3_CW_H 0x4E macro