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Searched refs:REG_CLKGEN0_BASE (Results 1 – 25 of 86) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h556 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
646 #define REG_CLKGEN0_BASE 0x100B00UL macro
653 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
654 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
677 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
686 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
695 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
708 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
721 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
729 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
[all …]
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h524 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
609 #define REG_CLKGEN0_BASE 0x100B00UL macro
616 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
617 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
637 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
646 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
655 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
668 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
681 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
689 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
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H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
378 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
379 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
380 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h569 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
658 #define REG_CLKGEN0_BASE 0x100B00UL macro
665 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
666 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
689 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
698 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
707 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
720 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
733 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
741 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
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H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h574 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
663 #define REG_CLKGEN0_BASE 0x100B00UL macro
670 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
671 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
694 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
703 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
712 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
725 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
738 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
746 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
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H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h560 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
650 #define REG_CLKGEN0_BASE 0x100B00UL macro
657 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
658 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
681 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
690 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
699 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
712 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
725 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
733 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
[all …]
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h465 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
550 #define REG_CLKGEN0_BASE 0x100B00UL macro
556 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
557 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
577 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
586 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
595 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
608 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
621 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
629 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
[all …]
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
378 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
379 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
380 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h511 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
599 #define REG_CLKGEN0_BASE 0x100B00UL macro
606 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
607 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
627 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
636 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
645 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
658 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
671 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB )
679 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF )
[all …]
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h390 #define REG_CLKGEN0_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
446 #define REG_CLKGEN0_BASE 0x100B00 macro
449 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
450 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
468 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
477 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
486 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
494 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
502 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if …
509 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk
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H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h390 #define REG_CLKGEN0_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
446 #define REG_CLKGEN0_BASE 0x100B00 macro
449 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
450 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
468 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
477 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
486 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
494 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
502 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if …
509 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk
[all …]
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
629 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
630 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
631 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h484 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
569 #define REG_CLKGEN0_BASE 0x100B00UL macro
575 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
576 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
596 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
607 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
616 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
628 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
641 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
649 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using,…
[all …]
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
378 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
379 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
380 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h482 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF macro
567 #define REG_CLKGEN0_BASE 0x100B00UL macro
573 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
574 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
594 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out
605 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out
614 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L
626 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L
639 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
647 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using,…
[all …]
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40)
378 #define REG_ADC_CLKGEN0_20_H (REG_CLKGEN0_BASE + 0x41)
379 #define REG_ADC_CLKGEN0_26_L (REG_CLKGEN0_BASE + 0x4C)
380 #define REG_ADC_CLKGEN0_26_H (REG_CLKGEN0_BASE + 0x4D)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.h172 #define REG_CLKGEN0_BASE 0x100B00 macro
195 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
196 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.h172 #define REG_CLKGEN0_BASE 0x100B00 macro
195 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
196 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h181 #define REG_CLKGEN0_BASE 0x100B00UL macro
203 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x)
204 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x)

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