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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef MHAL_XC_CONFIG_H 95 #define MHAL_XC_CONFIG_H 96 97 //------------------------------------------------------------------------------------------------- 98 // Monaco 99 //------------------------------------------------------------------------------------------------- 100 //------------------------------------------------------------------------------------------------- 101 // Chip Configuration 102 //------------------------------------------------------------------------------------------------- 103 #define MAX_XC_DEVICE_NUM (2) 104 #define MAX_XC_DEVICE0_OFFSET (0) 105 #define MAX_XC_DEVICE1_OFFSET (128) 106 107 #define MAX_WINDOW_NUM (2) 108 #define MAX_FRAME_NUM_IN_MEM (4) // Progressive 109 #define MAX_FIELD_NUM_IN_MEM (16) // Interlace 110 #define NUM_OF_DIGITAL_DDCRAM (1) 111 112 #define SCALER_LINE_BUFFER_MAX (4096UL) 113 #define MST_LINE_BFF_MAX MAX(4096, SCALER_LINE_BUFFER_MAX) 114 115 #define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 116 #define SUB_SCALER_LINE_BUFFER_MAX 2048UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 117 #define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 118 119 #define MS_3D_LINE_BFF_MAX (2048UL) 120 #define PHASE_OFFSET_LIMIT (0x2000UL) 121 #define PHASE_OFFSET_LIMIT_FREQ_ONLY (0x2000UL) //0x03DFUL // 0x8000UL 122 123 // MIU Word (Bytes) 124 #define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W 125 #define OFFSET_PIXEL_ALIGNMENT (64) 126 #define LPLL_LOOPGAIN (32) //due to bound cale. 127 #define LVDS_MPLL_CLOCK_MHZ (432) 128 #define FRC_OFFSET_PIXEL_ALIGNMENT (128) 129 130 #define FRC_BYTE_PER_WORD 32 131 #define MCDI_BYTE_PER_WORD 32 132 133 //value for pipe vcnt and hcnt delay 134 #define FRC_PIPE_DELAY_VCNT_FRC 0x10 135 #define FRC_PIPE_DELAY_HCNT_FRC 0x140 136 #define FRC_PIPE_DELAY_VCNT_FSC_FHD 0x1D 137 #define FRC_PIPE_DELAY_HCNT_FSC_FHD 0x140 138 #define FRC_PIPE_DELAY_VCNT_FSC_4K 0x0B 139 #define FRC_PIPE_DELAY_HCNT_FSC_4K 0x140 140 #define FRC_PIPE_DELAY_VCNT_FSC_4K_120Hz 0x0A 141 #define FRC_PIPE_DELAY_HCNT_FSC_4K_120Hz 0x140 142 143 #define DEFAULT_STEP_P 4 //conservative step value 144 #define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 145 #define STEP_P 2 //recommended step value -> more faster fpll(T3) 146 #define STEP_I ((STEP_P*STEP_P)/2) 147 #define IPGAIN_REFACTOR 5 148 149 #define F2_WRITE_LIMIT_EN BIT(31) //BK12_1b[15] 150 #define F2_WRITE_LIMIT_MIN BIT(30) //BK12_1b[14] 151 152 #define F1_WRITE_LIMIT_EN BIT(31) //BK12_5b[15] 153 #define F1_WRITE_LIMIT_MIN BIT(30) //BK12_5b[14] 154 155 #define F2_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_1b[15] 156 #define F1_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_5b[15] 157 158 #define F2_V_WRITE_LIMIT_EN BIT(15) //BK12_18[12] 159 #define F1_V_WRITE_LIMIT_EN BIT(15) //BK12_58[12] 160 161 #define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 162 #define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 163 164 #define ADC_MAX_CLK (3500) 165 166 #define SUPPORTED_XC_INT ((1UL << SC_INT_DIPW) | \ 167 (1UL << SC_INT_VSINT) | \ 168 (1UL << SC_INT_F2_VTT_CHG) | \ 169 (1UL << SC_INT_F1_VTT_CHG) | \ 170 (1UL << SC_INT_F2_VS_LOSE) | \ 171 (1UL << SC_INT_F1_VS_LOSE) | \ 172 (1UL << SC_INT_F2_JITTER) | \ 173 (1UL << SC_INT_F1_JITTER) | \ 174 (1UL << SC_INT_F2_IPVS_SB) | \ 175 (1UL << SC_INT_F1_IPVS_SB) | \ 176 (1UL << SC_INT_F2_IPHCS_DET) | \ 177 (1UL << SC_INT_F1_IPHCS_DET) | \ 178 (1UL << SC_INT_F2_HTT_CHG) | \ 179 (1UL << SC_INT_F1_HTT_CHG) | \ 180 (1UL << SC_INT_F2_HS_LOSE) | \ 181 (1UL << SC_INT_F1_HS_LOSE) | \ 182 (1UL << SC_INT_F2_CSOG) | \ 183 (1UL << SC_INT_F1_CSOG) | \ 184 (1UL << SC_INT_F2_ATP_READY) | \ 185 (1UL << SC_INT_F1_ATP_READY)) 186 187 188 //These table definition is from SC_BK0 spec. 189 //Because some chip development is different, it need to check and remap when INT function is used 190 191 #define IRQ_INT_DIPW 0 192 #define IRQ_INT_START 3 193 #define IRQ_INT_RESERVED1 IRQ_INT_START 194 195 #define IRQ_INT_VSINT 4 196 #define IRQ_INT_F2_VTT_CHG 5 197 #define IRQ_INT_F1_VTT_CHG 6 198 #define IRQ_INT_F2_VS_LOSE 7 199 #define IRQ_INT_F1_VS_LOSE 8 200 #define IRQ_INT_F2_JITTER 9 201 #define IRQ_INT_F1_JITTER 10 202 #define IRQ_INT_F2_IPVS_SB 11 203 #define IRQ_INT_F1_IPVS_SB 12 204 #define IRQ_INT_F2_IPHCS_DET 13 205 #define IRQ_INT_F1_IPHCS_DET 14 206 207 #define IRQ_INT_PWM_RP_L_INT 15 208 #define IRQ_INT_PWM_FP_L_INT 16 209 #define IRQ_INT_F2_HTT_CHG 17 210 #define IRQ_INT_F1_HTT_CHG 18 211 #define IRQ_INT_F2_HS_LOSE 19 212 #define IRQ_INT_F1_HS_LOSE 20 213 #define IRQ_INT_PWM_RP_R_INT 21 214 #define IRQ_INT_PWM_FP_R_INT 22 215 #define IRQ_INT_F2_CSOG 23 216 #define IRQ_INT_F1_CSOG 24 217 #define IRQ_INT_F2_RESERVED2 25 218 #define IRQ_INT_F1_RESERVED2 26 219 #define IRQ_INT_F2_ATP_READY 27 220 #define IRQ_INT_F1_ATP_READY 28 221 #define IRQ_INT_F2_RESERVED3 29 222 #define IRQ_INT_F1_RESERVED3 30 223 224 //------------------------------------------------------------------------------------------------- 225 // Chip Feature 226 //------------------------------------------------------------------------------------------------- 227 /* 12 frame mode for progessive */ 228 #define _12FRAME_BUFFER_PMODE_SUPPORTED 1 229 /* 8 frame mode for progessive */ 230 #define _8FRAME_BUFFER_PMODE_SUPPORTED 1 231 /* 6 frame mode for progessive */ 232 #define _6FRAME_BUFFER_PMODE_SUPPORTED 1 233 /* 4 frame mode for progessive */ 234 #define _4FRAME_BUFFER_PMODE_SUPPORTED 1 235 /* 3 frame mode for progessive */ 236 #define _3FRAME_BUFFER_PMODE_SUPPORTED 1 237 238 /* 239 Field-packing ( Customized name ) 240 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 241 IPM buffer address). We show one of memory format for example at below. 242 243 Block : Y0 C0 L M Y1 C1 244 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 245 Y0 has 64 * 4 bits ( 8 pixel for each field ). 246 Y1 has 64 * 4 bits ( 8 pixel for each field ). 247 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 248 For cropping, OPM address offset have to multiple 4. 249 */ 250 #define _FIELD_PACKING_MODE_SUPPORTED 1 251 252 #if (_FIELD_PACKING_MODE_SUPPORTED) 253 254 /* Linear mode */ 255 #define _LINEAR_ADDRESS_MODE_SUPPORTED 0 256 257 #else 258 /* Linear mode */ 259 #define _LINEAR_ADDRESS_MODE_SUPPORTED 1 260 261 #endif 262 263 #define SUPPORT_2_FRAME_MIRROR 0 264 265 /* Because fix loop_div, lpll initial set is different between singal port and dual port */ 266 #define _FIX_LOOP_DIV_SUPPORTED 1 267 268 // You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 269 // 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 270 #define ENABLE_8_FIELD_SUPPORTED 0 271 #define ENABLE_16_FIELD_SUPPORTED 1 272 #define ENABLE_OPM_WRITE_SUPPORTED 1 273 #define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 274 #define ENABLE_VD_PRESCALING_TO_DOT75 0 275 #define ENABLE_NONSTD_INPUT_MCNR 0 276 #define ENABLE_REGISTER_SPREAD 1 277 278 #define ENABLE_REQUEST_FBL 1 279 #define DELAY_LINE_SC_UP 7 280 #define DELAY_LINE_SC_DOWN 8 281 282 #define CHANGE_VTT_STEPS 1 283 #define CHANGE_VTT_DELAY 1 284 285 #define SUPPORT_IMMESWITCH 1 286 #define SUPPORT_DVI_AUTO_EQ 1 287 #define SUPPORT_MHL 0 288 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 289 #define SUPPORT_DEVICE1 0 290 #define SUPPORT_SEAMLESS_ZAPPING 0 291 #define SUPPORT_OP2_TEST_PATTERN 1 292 #define SUPPORT_FRCM_MODE 0 293 #define SUPPORT_4K2K_PIP 1 294 #define SUPPORT_KERNEL_DS 0 295 #define SUPPORT_KERNEL_MLOAD 0 296 297 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 298 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 299 300 #define LD_ENABLE 0 // 1 301 #define FRC_INSIDE TRUE //FALSE 302 #define FRC_IP_NUM_Passive 17 //FRC__NUM_FRC_Mapping_mode 303 304 // 480p and 576p have FPLL problem in HV mode. 305 // So only allow HV mode for 720P 306 #define ONLY_ALLOW_HV_MODE_FOR_720P 0 307 308 //For Manhattan U01 GOP HW bug //U02 Fix 309 #define MANHATTAN_GOP_HW_BUG_PATCH 1 310 311 #define _ENABLE_SW_DS 0 312 #define DS_BUFFER_NUM_EX 6 313 #define DS_MAX_INDEX 6 314 315 #define ENABLE_64BITS_COMMAND 1 316 #define ENABLE_64BITS_SPREAD_MODE 1 //need enable ENABLE_64BITS_COMMAND first 317 318 #define IS_SUPPORT_DS_SR(fps) 0 319 //------------------------------------------------------------------------------------------------- 320 /// enable ENABLE_MLOAD_SAME_REG_COMBINE you can do: 321 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(N), BIT(N)); 322 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(M), BIT(M)); 323 /// MApi_XC_MLoad_Fire(); 324 //------------------------------------------------------------------------------------------------- 325 #define ENABLE_MLOAD_SAME_REG_COMBINE 1 326 327 #define IS_SUPPORT_64BITS_COMMAND(bEnable64bitsCmd, u32DeviceID) ((bEnable64bitsCmd == 1) && (u32DeviceID == 0)) 328 #define ENABLE_DS_4_BASEADDR_MODE 1 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 329 #define DS_CMD_LEN_64BITS 8 330 331 // T12, T13 cannot use IP_HDMI for HV mode 332 // We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 333 //Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 334 // and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 335 // Thus, chip could use this flag to determine whether could do HV mode or not. 336 #define SUPPORT_IP_HDMI_FOR_HV_MODE 0 337 338 // version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 339 // version2: nike: 340 // version3: napoli: frc: double frc and width 341 // version4: monaco: frcm and 2p 342 // version5: clippers: 4k2k@60 MVOP directly output to HVSP 343 // version6: Monet/Maya/Manhattan: 344 // for Manhattan pip:1.SC1(1P) Htt = SC0(2P) Htt/2 345 // 2.if xc mute SC1 main, please mute SC0 sub. The same to mute color. 346 // 3.SC1 DE(bank 0x90) HStart = SC0 DE HStart/2, SC1 DE(bank 0x90) Width = SC0 DE Width/2 347 // 4.temp solution:SC0 DE VStart/Vend should add 6, so is SC1 DE Vstart/Vend 348 #define HW_DESIGN_4K2K_VER (6) 349 350 // version0: Not support TV chip as HDMITx 351 // version1: Maserati + Raptor 352 // version2: Maxim + inside HDMITx 353 #define HW_DESIGN_HDMITX_VER (0) 354 355 #define HW_DESIGN_3D_VER (3) 356 #define HW_2DTO3D_SUPPORT TRUE 357 #define HW_2DTO3D_VER (4) 358 #define HW_2DTO3D_BYTE_PER_WORD (32) 359 #define HW_2DTO3D_PATCH FALSE //a1 u01:2d to 3d hw bug 360 #define HW_2DTO3D_BLOCK_DR_BUF_SIZE (0x2200) 361 #define HW_2DTO3D_DD_BUF_SIZE (0xFF00) 362 //HW support check board and pixel alternative 363 #define HW_SUPPORT_3D_CB_AND_PA TRUE 364 #define ENABLE_GOP_T3DPATCH 365 #define VALUE_AUTO_TUNE_AREA_TRIG_4K540P (0x10) //4k0.5k 3D 366 #define VALUE_DISP_AREA_TRIG_4K540P (0x13) //4k0.5k 3D 367 368 //hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 369 #define HW_3D_SUPPORT_FBL TRUE 370 //M10, A2, J2 ,A5,A6,A3,Agate HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 371 //and for mirror cbcr swap, need check IPM fetch to decide if need swap 372 #define HW_IPM_FETCH_ALIGNMENT TRUE 373 //hw support 2 line mode deinterlace for interlace or not 374 #define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 375 #define HW_CLK_CTRL TRUE 376 #define SUPPORT_OSD_HSLVDS_PATH 1 377 #define MLG_1024 378 379 #define OSD_LAYER_NUM (5) 380 #define VIDEO_OSD_SWITCH_VER (2) 381 382 //#define FA_1920X540_OUTPUT 383 #define XC_SUPPORT_4K2K 1 384 385 // if H/W support 2p mode to achieve 600M HZ 386 #define XC_SUPPORT_2P_MODE TRUE 387 388 //device 1 is interlace out 389 #define XC_DEVICE1_IS_INTERLACE_OUT 0 390 391 //if H/W support force post-Vscalin-down in DS mode 392 #define HW_SUPPORT_FORCE_VSP_IN_DS_MODE TRUE 393 394 //if H/W support LPLL lock freqence not lock phase mode 395 #define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE TRUE 396 397 // if H/W support interlace output timing 398 #define HW_SUPPORT_INTERLACE_OUTPUT TRUE 399 400 // if H/W support 4k2k_60p output timing 401 #define HW_SUPPORT_4K2K_60P_OUTPUT TRUE 402 403 #define SUPPORT_MOD_ADBANK_SEPARATE 404 405 #define SUPPORT_FPLL_REFER_24MXTAL 406 407 // for 4K 0.5K 240Hz case, if input only 25fps, ivs:ovs = 5:48 case 408 #define SUPPORT_FPLL_DOUBLE_OVS 409 410 #define SUPPORT_HDMI20 1 411 412 #define LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 1 413 414 /// for Chip bringup 415 #define ENABLE_CHIP_BRINGUP 416 #define PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 1 // support pip&pop by multi sc ,such as sc1 support pip&pop 417 418 #define HW_4K2K_VIP_PEAKING_LIMITATION 0 419 #define HW_SCALING_LIMITATION 0 //NO LIMITATION 420 421 // support 3D DS 422 #define SUPPORT_3D_DS 0 423 424 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0) 425 //#define ENABLE_TV_SC2_PQ 426 #endif 427 //#define MONACO_SC2_PATCH 428 429 #define XC_SUPPORT_CMA TRUE 430 431 #define XC_CMA_8MB 0x0800000 432 #define XC_CMA_10MB 0x0A00000 433 #define XC_CMA_12MB 0x0C00000 434 #define XC_CMA_15MB 0x0F00000 435 #define XC_CMA_16MB 0x1000000 436 #define XC_CMA_18MB 0x1200000 437 #define XC_CMA_19MB 0x1300000 438 #define XC_CMA_20MB 0x1400000 439 #define XC_CMA_22MB 0x1600000 440 #define XC_CMA_24MB 0x1800000 441 #define XC_CMA_32MB 0x2000000 442 #define XC_CMA_36MB 0x2400000 443 #define XC_CMA_30MB 0x1E00000 444 #define XC_CMA_40MB 0x2800000 445 #define XC_CMA_48MB 0x3000000 446 #define XC_CMA_64MB 0x4000000 447 #define XC_CMA_72MB 0x4800000 448 #define XC_CMA_96MB 0x6000000 449 450 #define XC_4K2K_WIDTH_MAX 4500 451 #define XC_4K2K_WIDTH_MIN 3000 452 #define XC_4K2K_HIGH_MAX 2500 453 #define XC_4K2K_HIGH_MIN 1900 454 455 #define XC_4K1K_WIDTH_MAX 4500 456 #define XC_4K1K_WIDTH_MIN 3000 457 #define XC_4K1K_HIGH_MAX 1300 458 #define XC_4K1K_HIGH_MIN 900 459 460 #define XC_4K_HALFK_WIDTH_MAX 4500 // 4K 0.5K 461 #define XC_4K_HALFK_WIDTH_MIN 3000 // 4K 0.5K 462 #define XC_4K_HALFK_HIGH_MAX 600 // 4K 0.5K 463 #define XC_4K_HALFK_HIGH_MIN 500 // 4K 0.5K 464 465 #define XC_2K2K_WIDTH_MAX 2300 466 #define XC_2K2K_WIDTH_MIN 1500 467 #define XC_2K2K_HIGH_MAX 2500 468 #define XC_2K2K_HIGH_MIN 1900 469 470 #define XC_FHD_WIDTH_MAX 2300 471 #define XC_FHD_WIDTH_MIN 1500 472 #define XC_FHD_HIGH_MAX 1300 473 #define XC_FHD_HIGH_MIN 900 474 475 #define XC_FP1080P_H_SIZE 1920 476 #define XC_FP1080P_V_SIZE 2205 477 478 #define XC_FRC_IPM_L 0x2C4C000 // 4096x2160x1.5x7/2 479 #define XC_FRC_IPM_R 0x2C4C000 // 4096x2160x1.5x7/2 480 #define XC_FRC_MEDS_L 0x084E400 // 2048x1080x0.75x7/2x1.5 481 #define XC_FRC_MEDS_R 0x084E400 // 2048x1080x0.75x7/2x1.5 482 #define XC_FRC_ME1_X1 0x0061080 // 8x135x32x11.5 483 #define XC_FRC_ME1_S1 0x0030840 // 8x135x32x23 484 #define XC_FRC_ME2_X2 0x02D7BC0 // 30x270x32x11.5 485 #define XC_FRC_ME2_Y2 0x00C2100 // 8x270x32x11.5 486 #define XC_FRC_ME2_F2 0x01B4A40 // 18x270x32x11.5 487 #define XC_FRC_ME2_LOGO 0x00C2100 // 8x270x32x11.5 488 #define XC_FRC_HR 0x01FA400 // 40x270x32x6 489 #define XC_FRC_HR_BUF23 0x02F7600 // 30x270x32x12 490 491 492 493 //------------------------------------------------------------------------------------------------- 494 // Register base 495 //------------------------------------------------------------------------------------------------- 496 497 // PM 498 #define REG_DDC_BASE 0x000400UL 499 #define REG_PM_SLP_BASE 0x000E00UL 500 #define REG_PM_GPIO_BASE 0x000F00UL 501 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 502 #define REG_PAD_SAR_BASE 0x001400UL 503 #define REG_SCDC0_BASE 0x010200UL 504 #define REG_SCDC1_BASE 0x010300UL 505 #define REG_SCDC2_BASE 0x010400UL 506 #define REG_SCDC3_BASE 0x010500UL 507 #define REG_PM_TOP_BASE 0x001E00UL 508 #define REG_MHL_CBUS_BANK 0x001F00UL 509 #define REG_EFUSE_BASE 0x002000UL 510 #define REG_PM_MHL_CBUS_BANK 0x002F00UL 511 512 // NONPM 513 #define REG_MIU0_BASE 0x101200UL 514 #define REG_MIU0_EX_BASE 0x161500UL 515 #define REG_MIU0_ARBB_BASE 0x152000UL 516 #define REG_MIU1_BASE 0x100600UL 517 #define REG_MIU1_EX_BASE 0x162200UL 518 #define REG_MIU1_ARBB_BASE 0x152100UL 519 #define REG_MIU2_BASE 0x162000UL 520 #define REG_MIU2_EX_BASE 0x162300UL 521 #define REG_MIU2_ARBB_BASE 0x152200UL 522 523 #define REG_CLKGEN2_BASE 0x100A00UL 524 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF 525 #define REG_CHIP_BASE 0x101E00UL 526 #define REG_UHC0_BASE 0x102400UL 527 #define REG_UHC1_BASE 0x100D00UL 528 #define REG_ADC_ATOP_BASE 0x102500UL // 0x2500 - 0x25FF 529 #define REG_ADC_DTOP_BASE 0x102600UL // 0x2600 - 0x26EF 530 #define REG_ADC_CHIPTOP_BASE 0x101E00UL // 0x1E00 - 0x1EFF 531 #define REG_HDMI_BASE 0x102700UL // 0x2700 - 0x27FF 532 #define REG_CHIP_GPIO_BASE 0x102B00UL 533 #define REG_ADC_ATOPB_BASE 0x103D00UL // 0x3D00 - 0x3DFF 534 535 #define REG_HDMI2_BASE 0x101A00UL 536 #define REG_IPMUX_BASE 0x102E00UL 537 #define REG_MVOP_BASE 0x101400UL 538 #if ENABLE_REGISTER_SPREAD 539 #define REG_SCALER_BASE 0x130000UL 540 #else 541 #define REG_SCALER_BASE 0x102F00UL 542 #endif 543 #define REG_LPLL_BASE 0x103100UL 544 #define REG_MOD_BASE 0x103200UL 545 #define REG_PWM_BASE 0x13F400UL 546 #define REG_MOD_A_BASE 0x111E00UL 547 #define REG_AFEC_BASE 0x103500UL 548 #define REG_COMB_BASE 0x103600UL 549 550 #define REG_HDCPKEY_BASE 0x173800UL 551 #define REG_DVI_ATOP_BASE 0x110900UL 552 #define REG_DVI_DTOP_BASE 0x110A00UL 553 #define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 554 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 555 #define REG_ADC_DTOPB_BASE 0x111200UL // ADC DTOPB 556 #define REG_DVI_ATOP1_BASE 0x113200UL 557 #define REG_DVI_DTOP1_BASE 0x113300UL 558 #define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 559 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 560 #define REG_DVI_ATOP2_BASE 0x113400UL 561 #define REG_DVI_ATOP3_BASE 0x162F00UL 562 #define REG_DVI_DTOP2_BASE 0x113500UL 563 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 564 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 565 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving 566 #define REG_DVI_PS1_BASE 0x113640UL // DVI power saving1 567 #define REG_DVI_PS2_BASE 0x113680UL // DVI power saving2 568 #define REG_DVI_PS3_BASE 0x1136C0UL // DVI power saving3 569 #define REG_DVI_DTOP3_BASE 0x113700UL 570 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 571 #define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 572 573 #define REG_CHIP_ID_MAJOR 0x1ECC 574 #define REG_CHIP_ID_MINOR 0x1ECD 575 #define REG_CHIP_VERSION 0x1ECE 576 #define REG_CHIP_REVISION 0x1ECFUL 577 #define REG_CHIP_GPIO1_BASE 0x110300UL 578 579 #define REG_COMBO_PHY0_P0_BASE 0x170200UL 580 #define REG_COMBO_PHY1_P0_BASE 0x170300UL 581 #define REG_COMBO_PHY0_P1_BASE 0x170400UL 582 #define REG_COMBO_PHY1_P1_BASE 0x170500UL 583 #define REG_COMBO_PHY0_P2_BASE 0x170600UL 584 #define REG_COMBO_PHY1_P2_BASE 0x170700UL 585 #define REG_COMBO_PHY0_P3_BASE 0x170800UL 586 #define REG_COMBO_PHY1_P3_BASE 0x170900UL 587 588 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL 589 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL 590 #define REG_HDCP_DUAL_P0_BASE 0x171200UL 591 #define REG_DVI_DTOP_DUAL_P1_BASE 0x171300UL 592 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL 593 #define REG_HDCP_DUAL_P1_BASE 0x171500UL 594 #define REG_DVI_DTOP_DUAL_P2_BASE 0x171600UL 595 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL 596 #define REG_HDCP_DUAL_P2_BASE 0x171800UL 597 #define REG_DVI_DTOP_DUAL_P3_BASE 0x171900UL 598 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL 599 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL 600 601 #define REG_HDMI_DUAL_0_BASE 0x173000UL 602 #define REG_HDMI2_DUAL_0_BASE 0x173100UL 603 #define REG_HDMI3_DUAL_0_BASE 0x173400UL 604 605 #define REG_COMBO_GP_TOP_BASE 0x173900UL 606 #define REG_SECURE_TZPC_BASE 0x173A00UL 607 608 ////////////////////////// FRC using //////////////////////////////// 609 #define REG_CLKGEN0_BASE 0x100B00UL 610 #define REG_CLKGEN1_BASE 0x103300UL 611 612 ///FRC Area 613 #define REG_FSC_BANK_BASE 0x140000UL // FSC 0x102C bank, direct bank is 0x1400 614 #define REG_FRC_BANK_BASE 0x400000UL 615 616 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 617 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 618 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 619 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 620 /////////////////////////////////////////////////////////////////// 621 622 // store bank 623 #define LPLL_BK_STORE \ 624 MS_U8 u8Bank; \ 625 u8Bank = MDrv_ReadByte(REG_LPLL_BASE) 626 627 // restore bank 628 #define LPLL_BK_RESTORE MDrv_WriteByte(REG_LPLL_BASE, u8Bank) 629 630 // switch bank 631 #define LPLL_BK_SWITCH(_x_) MDrv_WriteByte(REG_LPLL_BASE, _x_) 632 633 634 //------------------------------------------------------------------------------ 635 // Register configure 636 //------------------------------------------------------------------------------ 637 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out 638 #define CKG_DACA2_GATED BIT(0) 639 #define CKG_DACA2_INVERT BIT(1) 640 #define CKG_DACA2_MASK BMASK(3:2) 641 #define CKG_DACA2_VIF_CLK (0 << 2) 642 #define CKG_DACA2_VD_CLK (1 << 2) 643 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 644 #define CKG_DACA2_XTAL (3 << 2) 645 646 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out 647 #define CKG_DACB2_GATED BIT(0) 648 #define CKG_DACB2_INVERT BIT(1) 649 #define CKG_DACB2_MASK BMASK(3:2) 650 #define CKG_DACB2_VIF_CLK (0 << 2) 651 #define CKG_DACB2_VD_CLK (1 << 2) 652 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 653 #define CKG_DACB2_XTAL (3 << 2) 654 655 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L 656 #define CKG_EDCLK_F1_GATED BIT(0) 657 #define CKG_EDCLK_F1_INVERT BIT(1) 658 #define CKG_EDCLK_F1_MASK BMASK(4:2) 659 #define CKG_EDCLK_F1_ADC (0 << 2) 660 #define CKG_EDCLK_F1_DVI (1 << 2) 661 #define CKG_EDCLK_F1_345MHZ (2 << 2) 662 #define CKG_EDCLK_F1_216MHZ (3 << 2) 663 #define CKG_EDCLK_F1_192MHZ (4 << 2) 664 #define CKG_EDCLK_F1_240MHZ (5 << 2) 665 #define CKG_EDCLK_F1_320MHZ (6 << 2) 666 #define CKG_EDCLK_F1_XTAL (7 << 2) 667 668 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L 669 #define CKG_EDCLK_F2_GATED BIT(0) 670 #define CKG_EDCLK_F2_INVERT BIT(1) 671 #define CKG_EDCLK_F2_MASK BMASK(4:2) 672 #define CKG_EDCLK_F2_ADC (0 << 2) 673 #define CKG_EDCLK_F2_DVI (1 << 2) 674 #define CKG_EDCLK_F2_345MHZ (2 << 2) 675 #define CKG_EDCLK_F2_216MHZ (3 << 2) 676 #define CKG_EDCLK_F2_192MHZ (4 << 2) 677 #define CKG_EDCLK_F2_240MHZ (5 << 2) 678 #define CKG_EDCLK_F2_320MHZ (6 << 2) 679 #define CKG_EDCLK_F2_XTAL (7 << 2) 680 681 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) 682 #define CKG_FMCLK_GATED BIT(0) 683 #define CKG_FMCLK_INVERT BIT(1) 684 #define CKG_FMCLK_MASK BMASK(3:2) 685 #define CKG_FMCLK_FCLK (0 << 2) 686 #define CKG_FMCLK_MIU_256 (1 << 2) 687 #define CKG_FMCLK_MIU_128 (2 << 2) 688 689 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) 690 #define CKG_SC_ROT_GATED BIT(0) 691 #define CKG_SC_ROT_INVERT BIT(1) 692 #define CKG_SC_ROT_MASK BMASK(3:2) 693 #define CKG_SC_ROT_MIU_256 (0 << 2) 694 #define CKG_SC_ROT_MIU_128 (1 << 2) 695 696 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 697 #define CKG_FICLK_F1_GATED BIT(0) 698 #define CKG_FICLK_F1_INVERT BIT(1) 699 #define CKG_FICLK_F1_MASK BMASK(3:2) 700 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 701 #define CKG_FICLK_F1_FLK (1 << 2) 702 //#define CKG_FICLK_F1_XTAL (3 << 2) 703 704 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using, not for FLCIK, and should set 0x00 for VE 705 #define CKG_FICLK_F2_GATED BIT(0) 706 #define CKG_FICLK_F2_INVERT BIT(1) 707 #define CKG_FICLK_F2_MASK BMASK(3:2) 708 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 709 #define CKG_FICLK_F2_FLK (0 << 2) 710 //#define CKG_FICLK_F2_XTAL (3 << 2) 711 712 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 713 #define CKG_FICLK2_F2_GATED BIT(4) 714 #define CKG_FICLK2_F2_INVERT BIT(5) 715 #define CKG_FICLK2_F2_MASK BMASK(7:6) 716 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 717 #define CKG_FICLK2_F2_FCLK (1 << 6) 718 719 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk 720 #define CKG_FCLK_GATED BIT(0) 721 #define CKG_FCLK_INVERT BIT(1) 722 #define CKG_FCLK_MASK BMASK(4:2) 723 #define CKG_FCLK_170MHZ (0 << 2) 724 #define CKG_FCLK_CLK_MIU (1 << 2) 725 #define CKG_FCLK_345MHZ (2 << 2) 726 #define CKG_FCLK_216MHZ (3 << 2) 727 #define CKG_FCLK_192MHZ (4 << 2) 728 #define CKG_FCLK_240MHZ (5 << 2) 729 #define CKG_FCLK_320MHZ (6 << 2) 730 #define CKG_FCLK_XTAL (7 << 2) 731 #define CKG_FCLK_XTAL_ CKG_FCLK_XTAL//(8 << 2) for A5 no XTAL 732 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ 733 734 #define REG_CKG_ODCLK (REG_CLKGEN0_BASE + 0xA6 ) // output dot clock, usually select LPLL, select XTAL when debug 735 #define CKG_ODCLK_GATED BIT(0) 736 #define CKG_ODCLK_INVERT BIT(1) 737 #define CKG_ODCLK_MASK BMASK(5:2) 738 #define CKG_ODCLK_SC_PLL (0 << 2) 739 #define CKG_ODCLK_LPLL_DIV2 (1 << 2) 740 #define CKG_ODCLK_27M (2 << 2) 741 #define CKG_ODCLK_CLK_LPLL (3 << 2) 742 //#define CKG_ODCLK_XTAL (8 << 2) 743 744 #define REG_CKG_IDCLK0 (REG_CLKGEN0_BASE + 0xA8 ) // off-line detect idclk 745 #define CKG_IDCLK0_GATED BIT(0) 746 #define CKG_IDCLK0_INVERT BIT(1) 747 #define CKG_IDCLK0_MASK BMASK(5:2) 748 #define CKG_IDCLK0_CLK_ADC (0 << 2) 749 #define CKG_IDCLK0_CLK_DVI (1 << 2) 750 #define CKG_IDCLK0_CLK_VD (2 << 2) 751 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 752 #define CKG_IDCLK0_ODCLK (4 << 2) 753 #define CKG_IDCLK0_0 (5 << 2) 754 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 755 #define CKG_IDCLK0_00 (7 << 2) // same as 5 --> also is 0 756 #define CKG_IDCLK0_XTAL CKG_IDCLK0_ODCLK//(8 << 2) for A5 no XTAL, select as OD 757 758 #define REG_CKG_IDCLK1 (REG_CLKGEN0_BASE + 0xA9 ) // sub main window idclk 759 #define CKG_IDCLK1_GATED BIT(0) 760 #define CKG_IDCLK1_INVERT BIT(1) 761 #define CKG_IDCLK1_MASK BMASK(5:2) 762 #define CKG_IDCLK1_CLK_ADC (0 << 2) 763 #define CKG_IDCLK1_CLK_DVI (1 << 2) 764 #define CKG_IDCLK1_CLK_VD (2 << 2) 765 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 766 #define CKG_IDCLK1_ODCLK (4 << 2) 767 #define CKG_IDCLK1_0 (5 << 2) 768 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 769 #define CKG_IDCLK1_00 (7 << 2) // same as 5 --> also is 0 770 #define CKG_IDCLK1_XTAL CKG_IDCLK1_ODCLK//(8 << 2) for A5 no XTAL,select as OD 771 772 #define REG_CKG_PRE_IDCLK1 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 773 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 774 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 775 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 776 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 777 778 #define REG_CKG_IDCLK2 (REG_CLKGEN0_BASE + 0xAA ) // main window idclk 779 #define CKG_IDCLK2_GATED BIT(0) 780 #define CKG_IDCLK2_INVERT BIT(1) 781 #define CKG_IDCLK2_MASK BMASK(5:2) 782 #define CKG_IDCLK2_CLK_ADC (0 << 2) 783 #define CKG_IDCLK2_CLK_DVI (1 << 2) 784 #define CKG_IDCLK2_CLK_VD (2 << 2) 785 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 786 #define CKG_IDCLK2_CLK_ADC2 (4 << 2) 787 #define CKG_IDCLK2_0 (5 << 2) 788 #define CKG_IDCLK2_00 (6 << 2) 789 #define CKG_IDCLK2_ODCLK (7 << 2) // same as 5 --> also is 0 790 #define CKG_IDCLK2_CLK_SUB_DC0 (8 << 2) 791 #define CKG_IDCLK2_CLK_ADC3 (9 << 2) 792 #define CKG_IDCLK2_ODCLK2 (10 << 2) 793 #define CKG_IDCLK2_CLKMHL (11 << 2) 794 #define CKG_IDCLK2_XTAL CKG_IDCLK2_ODCLK//(8 << 2)no XTAL select as OD 795 796 #define REG_CKG_PRE_IDCLK2 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 797 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 798 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 799 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 800 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 801 802 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + 0xB2 ) 803 #define CKG_IDCLK3_GATED BIT(0) 804 #define CKG_IDCLK3_INVERT BIT(1) 805 #define CKG_IDCLK3_MASK BMASK(5:2) 806 #define CKG_IDCLK3_CLK_ADC (0 << 2) 807 #define CKG_IDCLK3_CLK_DVI (1 << 2) 808 #define CKG_IDCLK3_CLK_VD (2 << 2) 809 #define CKG_IDCLK3_CLK_DC0 (3 << 2) 810 #define CKG_IDCLK3_ODCLK (4 << 2) 811 #define CKG_IDCLK3_0 (5 << 2) 812 #define CKG_IDCLK3_CLK_VD_ADC (6 << 2) 813 #define CKG_IDCLK3_00 (7 << 2) // same as 5 --> also is 0 814 #define CKG_IDCLK3_XTAL (8 << 2) 815 816 #define REG_CKG_IDCLK_USR_ENA (REG_CLKGEN0_BASE + 0xB4 ) // idclk user enable 817 #define CKG_IDCLK3_USR_ENA BIT(3) 818 819 820 #define REG_CKG_PRE_IDCLK3 (REG_CLKGEN0_BASE + 0xBC ) 821 #define CKG_PRE_IDCLK3_MASK BMASK(11:9) 822 #define CKG_PRE_IDCLK3_CLK_ADC (0 << 9) 823 #define CKG_PRE_IDCLK3_CLK_DVI (1 << 9) 824 #define CKG_PRE_IDCLK3_CLK_MHL (2 << 9) 825 826 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) 827 #define CKG_PDW0_GATED BIT(0) 828 #define CKG_PDW0_INVERT BIT(1) 829 #define CKG_PDW0_MASK BMASK(4:2) 830 #define CKG_PDW0_CLK_ADC (0 << 2) 831 #define CKG_PDW0_CLK_DVI (1 << 2) 832 #define CKG_PDW0_CLK_VD (2 << 2) 833 #define CKG_PDW0_CLK_DC0 (3 << 2) 834 #define CKG_PDW0_ODCLK (4 << 2) 835 #define CKG_PDW0_0 (5 << 2) 836 #define CKG_PDW0_CLK_VD_ADC (6 << 2) 837 #define CKG_PDW0_00 (7 << 2) // same as 5 --> also is 0 838 #define CKG_PDW0_XTAL (8 << 2) 839 840 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) 841 #define CKG_PDW1_GATED BIT(0) 842 #define CKG_PDW1_INVERT BIT(1) 843 #define CKG_PDW1_MASK BMASK(4:2) 844 #define CKG_PDW1_CLK_ADC (0 << 2) 845 #define CKG_PDW1_CLK_DVI (1 << 2) 846 #define CKG_PDW1_CLK_VD (2 << 2) 847 #define CKG_PDW1_CLK_DC0 (3 << 2) 848 #define CKG_PDW1_ODCLK (4 << 2) 849 #define CKG_PDW1_0 (5 << 2) 850 #define CKG_PDW1_CLK_VD_ADC (6 << 2) 851 #define CKG_PDW1_00 (7 << 2) // same as 5 --> also is 0 852 #define CKG_PDW1_XTAL (8 << 2) 853 854 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) 855 #define CKG_OSDC_GATED BIT(0) 856 #define CKG_OSDC_INVERT BIT(1) 857 #define CKG_OSDC_MASK BMASK(3:2) 858 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 859 860 #define REG_DE_ONLY_F3 (REG_CLKGEN0_BASE + 0xA0 ) 861 #define DE_ONLY_F3_MASK BIT(3) 862 863 #define REG_DE_ONLY_F2 (REG_CLKGEN0_BASE + 0xA0 ) 864 #define DE_ONLY_F2_MASK BIT(2) 865 866 #define REG_DE_ONLY_F1 (REG_CLKGEN0_BASE + 0xA0 ) 867 #define DE_ONLY_F1_MASK BIT(1) 868 869 #define REG_DE_ONLY_F0 (REG_CLKGEN0_BASE + 0xA0 ) 870 #define DE_ONLY_F0_MASK BIT(0) 871 872 873 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 874 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 875 876 #define REG_CLKGEN0_50_L (REG_CLKGEN0_BASE + 0xA0) 877 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) 878 #define REG_CLKGEN0_57_L (REG_CLKGEN0_BASE + 0xAE) 879 880 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 881 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x40) 882 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x41) 883 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x42) 884 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x43) 885 886 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 ) 887 #define CKG_S2_MECLK_GATED BIT(0) 888 #define CKG_S2_MECLK_INVERT BIT(1) 889 #define CKG_S2_MECLK_MASK BMASK(5:2) 890 891 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 ) 892 #define CKG_S2_MGCLK_GATED BIT(0) 893 #define CKG_S2_MGCLK_INVERT BIT(1) 894 #define CKG_S2_MGCLK_MASK BMASK(5:2) 895 896 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) 897 #define CKG_S2_GOP_HDR_GATED BIT(0) 898 #define CKG_S2_GOP_HDR_INVERT BIT(1) 899 #define CKG_S2_GOP_HDR_MASK BMASK(5:2) 900 #define CKG_S2_GOP_HDR_ODCLK (0 << 2) 901 #define CKG_S2_GOP_HDR_EDCLK (1 << 2) 902 903 //// for SC2, at REG_CLKGEN2_BASE 904 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 ) 905 #define CKG_S2_FICLK_F1_GATED BIT(0) 906 #define CKG_S2_FICLK_F1_INVERT BIT(1) 907 #define CKG_S2_FICLK_F1_MASK BMASK(3:2) 908 #define CKG_S2_FICLK_F1_IDCLK1 (0 << 2) 909 #define CKG_S2_FICLK_F1_FLK (1 << 2) 910 911 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 ) 912 #define CKG_S2_FICLK_F2_GATED BIT(0) 913 #define CKG_S2_FICLK_F2_INVERT BIT(1) 914 #define CKG_S2_FICLK_F2_MASK BMASK(3:2) 915 #define CKG_S2_FICLK_F2_IDCLK2 (0 << 2) 916 #define CKG_S2_FICLK_F2_FLK (1 << 2) 917 918 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) 919 #define CKG_S2_FICLK2_F2_GATED BIT(0) 920 #define CKG_S2_FICLK2_F2_INVERT BIT(1) 921 #define CKG_S2_FICLK2_F2_MASK BMASK(3:2) 922 #define CKG_S2_FICLK2_F2_IDCLK2 (0 << 2) // v prescaling 923 #define CKG_S2_FICLK2_F2_FCLK (1 << 2) // normal 924 #define CKG_S2_FICLK2_F2_MIUCLK (2 << 2) // DIP case 925 926 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk 927 #define CKG_S2_FCLK_GATED BIT(0) 928 #define CKG_S2_FCLK_INVERT BIT(1) 929 #define CKG_S2_FCLK_MASK BMASK(4:2) 930 #define CKG_S2_FCLK_172MHZ (0 << 2) 931 #define CKG_S2_FCLK_CLK_MIU (1 << 2) 932 #define CKG_S2_FCLK_345MHZ (2 << 2) 933 #define CKG_S2_FCLK_216MHZ (3 << 2) 934 #define CKG_S2_FCLK_192MHZ (4 << 2) 935 #define CKG_S2_FCLK_240MHZ (5 << 2) 936 #define CKG_S2_FCLK_320MHZ (6 << 2) 937 #define CKG_S2_FCLK_XTAL (7 << 2) 938 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ 939 940 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 ) 941 #define CKG_S2_FODCLK_GATED BIT(0) 942 #define CKG_S2_FODCLK_INVERT BIT(1) 943 #define CKG_S2_FODCLK_CLK_ODCLK (0 << 2) 944 #define CKG_S2_FODCLK_CLK_MIU (1 << 2) 945 946 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 ) 947 #define CKG_S2_ODCLK_GATED BIT(0) 948 #define CKG_S2_ODCLK_INVERT BIT(1) 949 #define CKG_S2_ODCLK_MASK BMASK(3:2) 950 #define CKG_S2_ODCLK_SYN_CLK (0 << 2) 951 #define CKG_S2_ODCLK_LPLL_DIV2 (1 << 2) 952 #define CKG_S2_ODCLK_27M (2 << 2) 953 #define CKG_S2_ODCLK_CLK_LPLL (3 << 2) 954 955 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk 956 #define CKG_S2_IDCLK0_GATED BIT(0) 957 #define CKG_S2_IDCLK0_INVERT BIT(1) 958 #define CKG_S2_IDCLK0_MASK BMASK(5:2) 959 #define CKG_S2_IDCLK0_CLK_ADC (0 << 2) 960 #define CKG_S2_IDCLK0_CLK_DVI (1 << 2) 961 #define CKG_S2_IDCLK0_CLK_VD (2 << 2) 962 #define CKG_S2_IDCLK0_CLK_DC0 (3 << 2) 963 #define CKG_S2_IDCLK0_CLK_ADC2 (4 << 2) 964 #define CKG_S2_IDCLK0_0 (5 << 2) 965 #define CKG_S2_IDCLK0_00 (6 << 2) 966 #define CKG_S2_IDCLK0_ODCLK (7 << 2) 967 #define CKG_S2_IDCLK0_CLK_SUB_DC0 (8 << 2) 968 #define CKG_S2_IDCLK0_CLK_ADC3 (9 << 2) 969 #define CKG_S2_IDCLK0_ODCLK2 (10<< 2) 970 #define CKG_S2_IDCLK0_MHL (13<< 2) 971 #define CKG_S2_IDCLK0_XTAL CKG_S2_IDCLK0_ODCLK 972 973 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk 974 #define CKG_S2_IDCLK1_GATED BIT(0) 975 #define CKG_S2_IDCLK1_INVERT BIT(1) 976 #define CKG_S2_IDCLK1_MASK BMASK(5:2) 977 #define CKG_S2_IDCLK1_CLK_ADC (0 << 2) 978 #define CKG_S2_IDCLK1_CLK_DVI (1 << 2) 979 #define CKG_S2_IDCLK1_CLK_VD (2 << 2) 980 #define CKG_S2_IDCLK1_CLK_DC0 (3 << 2) 981 #define CKG_S2_IDCLK1_CLK_ADC2 (4 << 2) 982 #define CKG_S2_IDCLK1_0 (5 << 2) 983 #define CKG_S2_IDCLK1_00 (6 << 2) 984 #define CKG_S2_IDCLK1_ODCLK (7 << 2) 985 #define CKG_S2_IDCLK1_CLK_SUB_DC0 (8 << 2) 986 #define CKG_S2_IDCLK1_CLK_ADC3 (9 << 2) 987 #define CKG_S2_IDCLK1_ODCLK2 (10<< 2) 988 #define CKG_S2_IDCLK1_MHL (13<< 2) 989 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK 990 991 #define REG_CKG_S2_IDCLK2 (REG_CLKGEN2_BASE + 0xCA ) // off-line detect idclk 992 #define CKG_S2_IDCLK2_GATED BIT(0) 993 #define CKG_S2_IDCLK2_INVERT BIT(1) 994 #define CKG_S2_IDCLK2_MASK BMASK(5:2) 995 #define CKG_S2_IDCLK2_CLK_ADC (0 << 2) 996 #define CKG_S2_IDCLK2_CLK_DVI (1 << 2) 997 #define CKG_S2_IDCLK2_CLK_VD (2 << 2) 998 #define CKG_S2_IDCLK2_CLK_DC0 (3 << 2) 999 #define CKG_S2_IDCLK2_CLK_ADC2 (4 << 2) 1000 #define CKG_S2_IDCLK2_0 (5 << 2) 1001 #define CKG_S2_IDCLK2_00 (6 << 2) 1002 #define CKG_S2_IDCLK2_ODCLK (7 << 2) 1003 #define CKG_S2_IDCLK2_CLK_SUB_DC0 (8 << 2) 1004 #define CKG_S2_IDCLK2_CLK_ADC3 (9 << 2) 1005 #define CKG_S2_IDCLK2_ODCLK2 (10<< 2) 1006 #define CKG_S2_IDCLK2_MHL (13<< 2) 1007 #define CKG_S2_IDCLK2_XTAL CKG_S2_IDCLK2_ODCLK 1008 1009 #define REG_CKG_S2_IDCLK3 (REG_CLKGEN2_BASE + 0xD2 ) // off-line detect idclk 1010 #define CKG_S2_IDCLK3_ATED BIT(0) 1011 #define CKG_S2_IDCLK3_INVERT BIT(1) 1012 #define CKG_S2_IDCLK3_MASK BMASK(5:2) 1013 #define CKG_S2_IDCLK3_CLK_ADC (0 << 2) 1014 #define CKG_S2_IDCLK3_CLK_DVI (1 << 2) 1015 #define CKG_S2_IDCLK3_CLK_VD (2 << 2) 1016 #define CKG_S2_IDCLK3_CLK_DC0 (3 << 2) 1017 #define CKG_S2_IDCLK3_CLK_ADC2 (4 << 2) 1018 #define CKG_S2_IDCLK3_0 (5 << 2) 1019 #define CKG_S2_IDCLK3_00 (6 << 2) 1020 #define CKG_S2_IDCLK3_ODCLK (7 << 2) 1021 #define CKG_S2_IDCLK3_CLK_SUB_DC0 (8 << 2) 1022 #define CKG_S2_IDCLK3_CLK_ADC3 (9 << 2) 1023 #define CKG_S2_IDCLK3_ODCLK2 (10<< 2) 1024 #define CKG_S2_IDCLK3_MHL (13<< 2) 1025 #define CKG_S2_IDCLK3_XTAL CKG_S2_IDCLK3_ODCLK 1026 1027 1028 #define REG_S2_DE_ONLY_F3 (REG_CLKGEN2_BASE + 0xC0 ) 1029 #define S2_DE_ONLY_F3_MASK BIT(3) 1030 1031 #define REG_S2_DE_ONLY_F2 (REG_CLKGEN2_BASE + 0xC0 ) 1032 #define S2_DE_ONLY_F2_MASK BIT(2) 1033 1034 #define REG_S2_DE_ONLY_F1 (REG_CLKGEN2_BASE + 0xC0 ) 1035 #define S2_DE_ONLY_F1_MASK BIT(1) 1036 1037 #define REG_S2_DE_ONLY_F0 (REG_CLKGEN2_BASE + 0xC0 ) 1038 #define S2_DE_ONLY_F0_MASK BIT(0) 1039 1040 //// 1041 #define CLK_SRC_IDCLK2 0 1042 #define CLK_SRC_FCLK 1 1043 #define CLK_SRC_XTAL 3 1044 1045 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 1046 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 1047 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 1048 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 1049 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06) 1050 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26) 1051 #define MIU0_G6_REQUEST_MASK (REG_MIU0_ARBB_BASE + 0x06) 1052 1053 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 1054 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 1055 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 1056 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 1057 #define MIU1_G4_REQUEST_MASK (REG_MIU1_EX_BASE + 0x06) 1058 #define MIU1_G5_REQUEST_MASK (REG_MIU1_EX_BASE + 0x26) 1059 #define MIU1_G6_REQUEST_MASK (REG_MIU1_ARBB_BASE + 0x06) 1060 1061 #define MIU2_G0_REQUEST_MASK (REG_MIU2_BASE + 0x46) 1062 #define MIU2_G1_REQUEST_MASK (REG_MIU2_BASE + 0x66) 1063 #define MIU2_G2_REQUEST_MASK (REG_MIU2_BASE + 0x86) 1064 #define MIU2_G3_REQUEST_MASK (REG_MIU2_BASE + 0xA6) 1065 #define MIU2_G4_REQUEST_MASK (REG_MIU2_EX_BASE + 0x06) 1066 #define MIU2_G5_REQUEST_MASK (REG_MIU2_EX_BASE + 0x26) 1067 #define MIU2_G6_REQUEST_MASK (REG_MIU2_ARBB_BASE + 0x06) 1068 1069 #define MIU_SC_G0REQUEST_MASK (0x0000) 1070 #define MIU_SC_G1REQUEST_MASK (0x0000) 1071 #define MIU_SC_G2REQUEST_MASK (0x0000) 1072 #define MIU_SC_G3REQUEST_MASK (0x0000) 1073 #define MIU_SC_G4REQUEST_MASK (0x0000) 1074 #define MIU_SC_G5REQUEST_MASK (0x0000) 1075 #define MIU_SC_G6REQUEST_MASK (0xF603) 1076 1077 ////////////////////////// FRC using //////////////////////////////// 1078 1079 #define MIU_FRC_G0REQUEST_MASK (0x0000) 1080 #define MIU_FRC_G1REQUEST_MASK (0x0000) 1081 #define MIU_FRC_G2REQUEST_MASK (0x0000) 1082 #define MIU_FRC_G3REQUEST_MASK (0x0000) 1083 #define MIU_FRC_G4REQUEST_MASK (0x0000) 1084 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) 1085 #define MIU_FRC_G6REQUEST_MASK (0x0000) 1086 1087 1088 1089 /////////////////////////////////////////////////////////////////// 1090 1091 #define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 1092 #define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 1093 #define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 1094 #define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 1095 1096 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 1097 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 1098 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 1099 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 1100 1101 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 1102 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 1103 1104 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 1105 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 1106 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 1107 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 1108 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 1109 1110 1111 #define HW_DESIGN_LD_VER (2) 1112 1113 #define FPLL_THRESH_MODE_SUPPORT 0 1114 1115 #define ADC_EFUSE_IN_MBOOT 1116 1117 #define ADC_CENTER_GAIN 0x1000 1118 #define ADC_CENTER_OFFSET 0x0800 1119 #define ADC_GAIN_BIT_CNT 14 1120 #define ADC_OFFSET_BIT_CNT 13 1121 1122 #define ADC_VGA_DEFAULT_GAIN_R 0x1000 1123 #define ADC_VGA_DEFAULT_GAIN_G 0x1000 1124 #define ADC_VGA_DEFAULT_GAIN_B 0x1000 1125 #define ADC_VGA_DEFAULT_OFFSET_R 0x0000 1126 #define ADC_VGA_DEFAULT_OFFSET_G 0x0000 1127 #define ADC_VGA_DEFAULT_OFFSET_B 0x0000 1128 #define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 1129 #define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 1130 #define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 1131 #define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 1132 #define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 1133 #define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 1134 #define ADC_SCART_DEFAULT_GAIN_R 0x1000 1135 #define ADC_SCART_DEFAULT_GAIN_G 0x1000 1136 #define ADC_SCART_DEFAULT_GAIN_B 0x1000 1137 #define ADC_SCART_DEFAULT_OFFSET_R 0x0100 1138 #define ADC_SCART_DEFAULT_OFFSET_G 0x0100 1139 #define ADC_SCART_DEFAULT_OFFSET_B 0x0100 1140 1141 /////////////////////////////////////////////// 1142 // Enable Hardware auto gain/offset 1143 #define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 1144 #define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 1145 #define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 1146 #define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 1147 #define ADC_VGA_FIXED_GAIN_R 0x1796 1148 #define ADC_VGA_FIXED_GAIN_G 0x1796 1149 #define ADC_VGA_FIXED_GAIN_B 0x1796 1150 #define ADC_VGA_FIXED_OFFSET_R 0x0000 1151 #define ADC_VGA_FIXED_OFFSET_G 0x0000 1152 #define ADC_VGA_FIXED_OFFSET_B 0x0000 1153 #define ADC_YPBPR_FIXED_GAIN_R 0x14B7 1154 #define ADC_YPBPR_FIXED_GAIN_G 0x1441 1155 #define ADC_YPBPR_FIXED_GAIN_B 0x14B7 1156 #define ADC_YPBPR_FIXED_OFFSET_R 0x0800 1157 #define ADC_YPBPR_FIXED_OFFSET_G 0x0100 1158 #define ADC_YPBPR_FIXED_OFFSET_B 0x0800 1159 #define ADC_SCART_FIXED_GAIN_R 0x1796 1160 #define ADC_SCART_FIXED_GAIN_G 0x1796 1161 #define ADC_SCART_FIXED_GAIN_B 0x1796 1162 #define ADC_SCART_FIXED_OFFSET_R 0x0000 1163 #define ADC_SCART_FIXED_OFFSET_G 0x0000 1164 #define ADC_SCART_FIXED_OFFSET_B 0x0000 1165 1166 #define SUPPORT_SC0_SUB_WIN FALSE 1167 #define SUPPORT_DUAL_MIU_MIRROR_SWAP_IPM TRUE 1168 #endif /* MHAL_XC_CONFIG_H */ 1169 1170