| /utopia/UTPA2-700.0.x/modules/miu/hal/curry/miu/ |
| H A D | halMIU.c | 975 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
988 uRegBase = MIU_ATOP_BASE+0x80; in HAL_MIU_SetSsc()
998 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/k6/miu/ |
| H A D | halMIU.c | 1407 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1417 uRegBase = MIU_ATOP_BASE+0x80; in HAL_MIU_SetSsc()
1427 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/ |
| H A D | halMIU.c | 1407 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1417 uRegBase = MIU_ATOP_BASE+0x80; in HAL_MIU_SetSsc()
1427 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/k6lite/miu/ |
| H A D | halMIU.c | 1406 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1416 uRegBase = MIU_ATOP_BASE+0x80; in HAL_MIU_SetSsc()
1426 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/k7u/miu/ |
| H A D | halMIU.c | 1407 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1417 uRegBase = MIU_ATOP_BASE+0x80; in HAL_MIU_SetSsc()
1427 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/M7621/miu/ |
| H A D | regMIU.h | 119 #define MIU_ATOP_BASE (0x10D00UL) macro
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| H A D | halMIU.c | 1239 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1247 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| /utopia/UTPA2-700.0.x/modules/miu/hal/mustang/miu/ |
| H A D | regMIU.h | 119 #define MIU_ATOP_BASE (0x10D00) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/maxim/miu/ |
| H A D | regMIU.h | 119 #define MIU_ATOP_BASE (0x10D00UL) macro
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| H A D | halMIU.c | 1233 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1241 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| /utopia/UTPA2-700.0.x/modules/miu/hal/maldives/miu/ |
| H A D | regMIU.h | 120 #define MIU_ATOP_BASE (0x10D00) macro
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| H A D | halMIU.c | 1157 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1165 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| /utopia/UTPA2-700.0.x/modules/miu/hal/messi/miu/ |
| H A D | regMIU.h | 101 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/mooney/miu/ |
| H A D | regMIU.h | 101 #define MIU_ATOP_BASE (0x10D00UL) macro
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| H A D | halMIU.c | 1312 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
1320 uRegBase = MIU_ATOP_BASE; in HAL_MIU_SetSsc()
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| /utopia/UTPA2-700.0.x/modules/miu/hal/mainz/miu/ |
| H A D | regMIU.h | 101 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/ |
| H A D | regMIU.h | 122 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/ |
| H A D | regMIU.h | 122 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/ |
| H A D | regMIU.h | 122 #define MIU_ATOP_BASE (0x10D00UL) macro
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| /utopia/UTPA2-700.0.x/modules/miu/hal/macan/miu/ |
| H A D | regMIU.h | 122 #define MIU_ATOP_BASE (0x10D00UL) macro
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