1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
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14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
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32 //
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55 //
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74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 //-------------------------------------------------------------------------------------------------
80 // Include Files
81 //-------------------------------------------------------------------------------------------------
82 #include "MsCommon.h"
83 #include "MsTypes.h"
84 #include "drvMIU.h"
85 #include "regMIU.h"
86 #include "halMIU.h"
87 #include "halCHIP.h"
88
89 //-------------------------------------------------------------------------------------------------
90 // Driver Compiler Options
91 //-------------------------------------------------------------------------------------------------
92
93
94 //-------------------------------------------------------------------------------------------------
95 // Local Defines
96 //-------------------------------------------------------------------------------------------------
97 #define MIU_HAL_ERR(x, args...) {printf(x, ##args);}
98 #define HAL_MIU_SSC_DBG(x) //x
99
100 #define MIU_CLIENT_GP0 \
101 /* 0 */ MIU_CLIENT_NONE, \
102 /* 1 */ MIU_CLIENT_VIVALDI9_DECODER_RW, \
103 /* 2 */ MIU_CLIENT_AU_R2_RW, \
104 /* 3 */ MIU_CLIENT_VD_R2I_R, \
105 /* 4 */ MIU_CLIENT_SECURE_R2_RW, \
106 /* 5 */ MIU_CLIENT_VD_R2D_RW, \
107 /* 6 */ MIU_CLIENT_DUMMY, \
108 /* 7 */ MIU_CLIENT_VD_R2_L_I_R, \
109 /* 8 */ MIU_CLIENT_VD_R2_L_D_RW, \
110 /* 9 */ MIU_CLIENT_TSP03_RW, \
111 /* A */ MIU_CLIENT_MVD_BBU_RW, \
112 /* B */ MIU_CLIENT_DUMMY, \
113 /* C */ MIU_CLIENT_XD2MIU_RW, \
114 /* D */ MIU_CLIENT_UART_DMA_RW, \
115 /* E */ MIU_CLIENT_BDMA_RW, \
116 /* F */ MIU_CLIENT_DUMMY
117
118 #define MIU_CLIENT_GP1 \
119 /* 0 */ MIU_CLIENT_VIVALDI9_DMA_RW, \
120 /* 1 */ MIU_CLIENT_DUMMY, \
121 /* 2 */ MIU_CLIENT_DUMMY, \
122 /* 3 */ MIU_CLIENT_CA_MIU_CROSSBAR_2_RW,\
123 /* 4 */ MIU_CLIENT_TSP06_RW, \
124 /* 5 */ MIU_CLIENT_TSP07_RW, \
125 /* 6 */ MIU_CLIENT_TSP08_RW, \
126 /* 7 */ MIU_CLIENT_DUMMY, \
127 /* 8 */ MIU_CLIENT_DUMMY, \
128 /* 9 */ MIU_CLIENT_USB_UHC1_RW, \
129 /* A */ MIU_CLIENT_USB_UHC2_RW, \
130 /* B */ MIU_CLIENT_DUMMY, \
131 /* C */ MIU_CLIENT_DUMMY, \
132 /* D */ MIU_CLIENT_TSP04_RW, \
133 /* E */ MIU_CLIENT_TSP05_RW, \
134 /* F */ MIU_CLIENT_DUMMY
135
136 #define MIU_CLIENT_GP2 \
137 /* 0 */ MIU_CLIENT_SDIO_RW, \
138 /* 1 */ MIU_CLIENT_DUMMY, \
139 /* 2 */ MIU_CLIENT_DUMMY, \
140 /* 3 */ MIU_CLIENT_DUMMY, \
141 /* 4 */ MIU_CLIENT_DUMMY, \
142 /* 5 */ MIU_CLIENT_DUMMY, \
143 /* 6 */ MIU_CLIENT_MVD_RW, \
144 /* 7 */ MIU_CLIENT_JPD_RW, \
145 /* 8 */ MIU_CLIENT_GMAC_RW, \
146 /* 9 */ MIU_CLIENT_NAND_RW, \
147 /* A */ MIU_CLIENT_EMAC_RW, \
148 /* B */ MIU_CLIENT_GPD_RW, \
149 /* C */ MIU_CLIENT_DUMMY, \
150 /* D */ MIU_CLIENT_DUMMY, \
151 /* E */ MIU_CLIENT_DUMMY, \
152 /* F */ MIU_CLIENT_DUMMY
153
154 #define MIU_CLIENT_GP3 \
155 /* 0 */ MIU_CLIENT_DUMMY, \
156 /* 1 */ MIU_CLIENT_DUMMY, \
157 /* 2 */ MIU_CLIENT_CMD_QUEUE_R, \
158 /* 3 */ MIU_CLIENT_USB_UHC0_RW, \
159 /* 4 */ MIU_CLIENT_DUMMY, \
160 /* 5 */ MIU_CLIENT_ZDEC_ACP_W, \
161 /* 6 */ MIU_CLIENT_DUMMY, \
162 /* 7 */ MIU_CLIENT_ZDEC_LZDMA_RW, \
163 /* 8 */ MIU_CLIENT_MFE1_R, \
164 /* 9 */ MIU_CLIENT_DUMMY, \
165 /* A */ MIU_CLIENT_MFE0_W, \
166 /* B */ MIU_CLIENT_DUMMY, \
167 /* C */ MIU_CLIENT_DUMMY, \
168 /* D */ MIU_CLIENT_DUMMY, \
169 /* E */ MIU_CLIENT_DUMMY, \
170 /* F */ MIU_CLIENT_DUMMY
171
172 #define MIU_CLIENT_GP4 \
173 /* 0 */ MIU_CLIENT_DUMMY, \
174 /* 1 */ MIU_CLIENT_DUMMY, \
175 /* 2 */ MIU_CLIENT_DUMMY, \
176 /* 3 */ MIU_CLIENT_DUMMY, \
177 /* 4 */ MIU_CLIENT_HVD_RW, \
178 /* 5 */ MIU_CLIENT_DUMMY, \
179 /* 6 */ MIU_CLIENT_EVD2_BBU_R, \
180 /* 7 */ MIU_CLIENT_EVD_RW, \
181 /* 8 */ MIU_CLIENT_DUMMY, \
182 /* 9 */ MIU_CLIENT_MVD_RTO_RW, \
183 /* A */ MIU_CLIENT_EVD_BBU_R, \
184 /* B */ MIU_CLIENT_HVD_BBU_R, \
185 /* C */ MIU_CLIENT_SC1_IPMAIN_RW, \
186 /* D */ MIU_CLIENT_SC1_OPM_R, \
187 /* E */ MIU_CLIENT_DUMMY, \
188 /* F */ MIU_CLIENT_DUMMY
189
190 #define MIU_CLIENT_GP5 \
191 /* 0 */ MIU_CLIENT_GOP0_R, \
192 /* 1 */ MIU_CLIENT_GOP1_R, \
193 /* 2 */ MIU_CLIENT_GOP2_R, \
194 /* 3 */ MIU_CLIENT_GOP3_DWIN_RW, \
195 /* 4 */ MIU_CLIENT_MVOP_256BIT_R, \
196 /* 5 */ MIU_CLIENT_DUMMY, \
197 /* 6 */ MIU_CLIENT_SC_IPMAIN_RW, \
198 /* 7 */ MIU_CLIENT_SC_IPSUB_RW, \
199 /* 8 */ MIU_CLIENT_SC_OPM_R, \
200 /* 9 */ MIU_CLIENT_SC_DIPW_RW, \
201 /* A */ MIU_CLIENT_MFDEC_R, \
202 /* B */ MIU_CLIENT_MFDEC1_R, \
203 /* C */ MIU_CLIENT_SC_DYN_SCL_R, \
204 /* D */ MIU_CLIENT_DUMMY, \
205 /* E */ MIU_CLIENT_VE_R, \
206 /* F */ MIU_CLIENT_GE_RW
207
208 #define MIU_CLIENT_GP6 \
209 /* 0 */ MIU_CLIENT_DUMMY, \
210 /* 1 */ MIU_CLIENT_DUMMY, \
211 /* 2 */ MIU_CLIENT_DUMMY, \
212 /* 3 */ MIU_CLIENT_DUMMY, \
213 /* 4 */ MIU_CLIENT_DUMMY, \
214 /* 5 */ MIU_CLIENT_DUMMY, \
215 /* 6 */ MIU_CLIENT_DUMMY, \
216 /* 7 */ MIU_CLIENT_DUMMY, \
217 /* 8 */ MIU_CLIENT_DUMMY, \
218 /* 9 */ MIU_CLIENT_DUMMY, \
219 /* A */ MIU_CLIENT_DUMMY, \
220 /* B */ MIU_CLIENT_DUMMY, \
221 /* C */ MIU_CLIENT_DUMMY, \
222 /* D */ MIU_CLIENT_DUMMY, \
223 /* E */ MIU_CLIENT_DUMMY, \
224 /* F */ MIU_CLIENT_DUMMY
225
226 #define MIU_CLIENT_GP7 \
227 /* 0 */ MIU_CLIENT_MIPS_RW, \
228 /* 1 */ MIU_CLIENT_G3D_RW, \
229 /* 2 */ MIU_CLIENT_DUMMY, \
230 /* 3 */ MIU_CLIENT_DUMMY, \
231 /* 4 */ MIU_CLIENT_DUMMY, \
232 /* 5 */ MIU_CLIENT_DUMMY, \
233 /* 6 */ MIU_CLIENT_DUMMY, \
234 /* 7 */ MIU_CLIENT_DUMMY, \
235 /* 8 */ MIU_CLIENT_DUMMY, \
236 /* 9 */ MIU_CLIENT_DUMMY, \
237 /* A */ MIU_CLIENT_DUMMY, \
238 /* B */ MIU_CLIENT_DUMMY, \
239 /* C */ MIU_CLIENT_DUMMY, \
240 /* D */ MIU_CLIENT_DUMMY, \
241 /* E */ MIU_CLIENT_DUMMY, \
242 /* F */ MIU_CLIENT_DUMMY
243
244 #define KHz (1000UL)
245 #define MHz (1000000UL)
246 #define MPPL (432)
247 #define DDR_FACTOR (524288)
248 #define DDFSPAN_FACTOR (131072)
249 #define IDNUM_KERNELPROTECT (8)
250
251 //-------------------------------------------------------------------------------------------------
252 // Local Structures
253 //-------------------------------------------------------------------------------------------------
254 const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] =
255 {
256 {
257 MIU_CLIENT_GP0,
258 MIU_CLIENT_GP1,
259 MIU_CLIENT_GP2,
260 MIU_CLIENT_GP3,
261 MIU_CLIENT_GP4,
262 MIU_CLIENT_GP5,
263 MIU_CLIENT_GP6,
264 MIU_CLIENT_GP7
265 }
266 };
267
268 MS_U8 clientId_KernelProtect[IDNUM_KERNELPROTECT] =
269 {
270 MIU_CLIENT_MIPS_RW,
271 MIU_CLIENT_NAND_RW,
272 MIU_CLIENT_USB_UHC0_RW,
273 MIU_CLIENT_USB_UHC1_RW,
274 MIU_CLIENT_USB_UHC2_RW,
275 MIU_CLIENT_USB3_RW,
276 MIU_CLIENT_NONE,
277 MIU_CLIENT_NONE
278 };
279 //-------------------------------------------------------------------------------------------------
280 // Global Variables
281 //-------------------------------------------------------------------------------------------------
282
283 //-------------------------------------------------------------------------------------------------
284 // Local Variables
285 //-------------------------------------------------------------------------------------------------
286 static MS_VIRT _gMIU_MapBase = 0x1f200000;
287 static MS_VIRT _gPM_MapBase = 0x1f000000;
288
289 MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] =
290 {
291 {{0}, {0}, {0}, {0}}
292 }; //ID enable for protect block 0~3
293
294 MS_U8 IDs[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] =
295 {
296 {0}
297 }; //IDs for protection
298
299 //-------------------------------------------------------------------------------------------------
300 // Debug Functions
301 //-------------------------------------------------------------------------------------------------
302
303 //-------------------------------------------------------------------------------------------------
304 // Local Functions
305 //-------------------------------------------------------------------------------------------------
306
307 //-------------------------------------------------------------------------------------------------
308 // Type and Structure Declaration
309 //-------------------------------------------------------------------------------------------------
310
311 //-------------------------------------------------------------------------------------------------
312 // Global Functions
313 //-------------------------------------------------------------------------------------------------
HAL_MIU_SetIOMapBase(MS_VIRT virtBase)314 void HAL_MIU_SetIOMapBase(MS_VIRT virtBase)
315 {
316 _gMIU_MapBase = virtBase;
317 HAL_MIU_SSC_DBG(printf("MIU _gMIU_MapBase= %lx\n", _gMIU_MapBase));
318 }
319
HAL_MIU_SetPMIOMapBase(MS_VIRT virtBase)320 void HAL_MIU_SetPMIOMapBase(MS_VIRT virtBase)
321 {
322 _gPM_MapBase = virtBase;
323 HAL_MIU_SSC_DBG(printf("MIU _gPM_MapBase= %lx\n", _gPM_MapBase));
324 }
325
HAL_MIU_GetClientInfo(MS_U8 u8MiuDev,eMIUClientID eClientID)326 MS_S16 HAL_MIU_GetClientInfo(MS_U8 u8MiuDev, eMIUClientID eClientID)
327 {
328 MS_U8 idx;
329
330 if (MIU_MAX_DEVICE <= u8MiuDev)
331 {
332 printf("Wrong MIU device:%u\n", u8MiuDev);
333 return (-1);
334 }
335
336 for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++)
337 if (eClientID == clientTbl[u8MiuDev][idx])
338 return idx;
339 return (-1);
340 }
341
342 ////////////////////////////////////////////////////////////////////////////////
343 /// @brief \b Function \b Name: HAL_MIU_ReadByte
344 /// @brief \b Function \b Description: read 1 Byte data
345 /// @param <IN> \b u32RegAddr: register address
346 /// @param <OUT> \b None :
347 /// @param <RET> \b MS_U8
348 /// @param <GLOBAL> \b None :
349 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ReadByte(MS_U32 u32RegAddr)350 MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegAddr)
351 {
352 return ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
353 }
354
355
356 ////////////////////////////////////////////////////////////////////////////////
357 /// @brief \b Function \b Name: HAL_MIU_PM_ReadByte
358 /// @brief \b Function \b Description: read 1 Byte data
359 /// @param <IN> \b u32RegAddr: register address
360 /// @param <OUT> \b None :
361 /// @param <RET> \b MS_U8
362 /// @param <GLOBAL> \b None :
363 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)364 MS_U8 HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)
365 {
366 return ((volatile MS_U8*)(_gPM_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
367 }
368
369 ////////////////////////////////////////////////////////////////////////////////
370 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
371 /// @brief \b Function \b Description: read 2 Byte data
372 /// @param <IN> \b u32RegAddr: register address
373 /// @param <OUT> \b None :
374 /// @param <RET> \b MS_U16
375 /// @param <GLOBAL> \b None :
376 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read2Byte(MS_U32 u32RegAddr)377 MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegAddr)
378 {
379 return ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr];
380 }
381
382
383 ////////////////////////////////////////////////////////////////////////////////
384 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
385 /// @brief \b Function \b Description: read 4 Byte data
386 /// @param <IN> \b u32RegAddr: register address
387 /// @param <OUT> \b None :
388 /// @param <RET> \b MS_U32
389 /// @param <GLOBAL> \b None :
390 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read4Byte(MS_U32 u32RegAddr)391 MS_U32 HAL_MIU_Read4Byte(MS_U32 u32RegAddr)
392 {
393 return (HAL_MIU_Read2Byte(u32RegAddr) | HAL_MIU_Read2Byte(u32RegAddr+2) << 16);
394 }
395
396
397 ////////////////////////////////////////////////////////////////////////////////
398 /// @brief \b Function \b Name: HAL_MIU_WriteByte
399 /// @brief \b Function \b Description: write 1 Byte data
400 /// @param <IN> \b u32RegAddr: register address
401 /// @param <IN> \b u8Val : 1 byte data
402 /// @param <OUT> \b None :
403 /// @param <RET> \b TRUE: Ok FALSE: Fail
404 /// @param <GLOBAL> \b None :
405 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)406 MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
407 {
408 if (!u32RegAddr)
409 {
410 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
411 return FALSE;
412 }
413
414 ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
415 return TRUE;
416 }
417
418
419 ////////////////////////////////////////////////////////////////////////////////
420 /// @brief \b Function \b Name: HAL_MIU_Write2Byte
421 /// @brief \b Function \b Description: write 2 Byte data
422 /// @param <IN> \b u32RegAddr: register address
423 /// @param <IN> \b u16Val : 2 byte data
424 /// @param <OUT> \b None :
425 /// @param <RET> \b TRUE: Ok FALSE: Fail
426 /// @param <GLOBAL> \b None :
427 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)428 MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
429 {
430 if (!u32RegAddr)
431 {
432 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
433 return FALSE;
434 }
435
436 ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr] = u16Val;
437 return TRUE;
438 }
439
440
441 ////////////////////////////////////////////////////////////////////////////////
442 /// @brief \b Function \b Name: HAL_BDMA_Write4Byte
443 /// @brief \b Function \b Description: write 4 Byte data
444 /// @param <IN> \b u32RegAddr: register address
445 /// @param <IN> \b u32Val : 4 byte data
446 /// @param <OUT> \b None :
447 /// @param <RET> \b TRUE: Ok FALSE: Fail
448 /// @param <GLOBAL> \b None :
449 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)450 MS_BOOL HAL_MIU_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
451 {
452 if (!u32RegAddr)
453 {
454 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
455 return FALSE;
456 }
457
458 HAL_MIU_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
459 HAL_MIU_Write2Byte(u32RegAddr+2, u32Val >> 16);
460 return TRUE;
461 }
462
463
464 ////////////////////////////////////////////////////////////////////////////////
465 /// @brief \b Function \b Name: HAL_BDMA_WriteByte
466 /// @brief \b Function \b Description: write 1 Byte data
467 /// @param <IN> \b u32RegAddr: register address
468 /// @param <IN> \b u8Val : 1 byte data
469 /// @param <OUT> \b None :
470 /// @param <RET> \b TRUE: Ok FALSE: Fail
471 /// @param <GLOBAL> \b None :
472 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask,MS_BOOL bEnable)473 MS_BOOL HAL_MIU_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable)
474 {
475 MS_U8 u8Val = HAL_MIU_ReadByte(u32RegAddr);
476 if (!u32RegAddr)
477 {
478 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
479 return FALSE;
480 }
481
482 u8Val = HAL_MIU_ReadByte(u32RegAddr);
483 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
484 HAL_MIU_WriteByte(u32RegAddr, u8Val);
485 return TRUE;
486 }
487
HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset,MS_BOOL bEnable,MS_U16 u16Mask)488 void HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset, MS_BOOL bEnable, MS_U16 u16Mask)
489 {
490 MS_U16 val = HAL_MIU_Read2Byte(u32RegOffset);
491 val = (bEnable) ? (val | u16Mask) : (val & ~u16Mask);
492 HAL_MIU_Write2Byte(u32RegOffset, val);
493 }
494
HAL_MIU_SetProtectID(MS_U32 u32Reg,MS_U8 u8MiuDev,MS_U8 u8ClientID)495 void HAL_MIU_SetProtectID(MS_U32 u32Reg, MS_U8 u8MiuDev, MS_U8 u8ClientID)
496 {
497 MS_S16 sVal;
498 MS_S16 sIDVal;
499
500 if (MIU_MAX_DEVICE <= u8MiuDev)
501 return;
502
503 sVal = HAL_MIU_GetClientInfo(u8MiuDev, (eMIUClientID)u8ClientID);
504
505 if (0 > sVal)
506 sVal = 0;
507
508 sIDVal = HAL_MIU_ReadByte(u32Reg);
509 sIDVal &= 0x80;
510 sIDVal |= sVal;
511 HAL_MIU_WriteByte(u32Reg, sIDVal);
512 }
513
HAL_MIU_SetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)514 MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
515 {
516 MS_U32 u32index0, u32index1;
517 MS_U8 u8ID;
518 MS_U8 u8isfound0, u8isfound1;
519 MS_U16 u16idenable;
520
521 if (MIU_MAX_DEVICE <= u8MiuSel)
522 return FALSE;
523
524 //reset IDenables for protect u8Blockx
525 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
526 {
527 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
528 }
529
530 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
531 {
532 u8ID = pu8ProtectId[u32index0];
533
534 //Unused ID
535 if(u8ID == 0)
536 continue;
537
538 u8isfound0 = FALSE;
539
540 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
541 {
542 if(IDs[u8MiuSel][u32index1] == u8ID)
543 {
544 //ID reused former setting
545 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
546 u8isfound0 = TRUE;
547 break;
548 }
549 }
550
551
552 //Need to create new ID in IDs
553 if(u8isfound0 != TRUE)
554 {
555 u8isfound1 = FALSE;
556
557 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
558 {
559 if(IDs[u8MiuSel][u32index1] == 0)
560 {
561 IDs[u8MiuSel][u32index1] = u8ID;
562 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
563 u8isfound1 = TRUE;
564 break;
565 }
566 }
567
568 //ID overflow
569 if(u8isfound1 == FALSE)
570 return FALSE;
571 }
572 }
573
574 u16idenable = 0;
575
576 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
577 {
578 if(IDEnables[u8MiuSel][u8Blockx][u32index0] == 1)
579 u16idenable |= (1<<u32index0);
580 }
581
582 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
583
584 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
585 {
586 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, (u8MiuSel== E_MIU_1), IDs[u8MiuSel][u32index0]);
587 }
588
589 return TRUE;
590 }
591
HAL_MIU_ResetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)592 MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
593 {
594 MS_U32 u32index0, u32index1;
595 MS_U8 u8isIDNoUse;
596 MS_U16 u16idenable;
597
598 if (MIU_MAX_DEVICE <= u8MiuSel)
599 return FALSE;
600
601 //reset IDenables for protect u8Blockx
602 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
603 {
604 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
605 }
606
607 u16idenable = 0x0;
608
609 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
610
611 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
612 {
613 u8isIDNoUse = FALSE;
614
615 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++)
616 {
617 if(IDEnables[u8MiuSel][u32index1][u32index0] == 1)
618 {
619 //protect ID is still be used
620 u8isIDNoUse = FALSE;
621 break;
622 }
623 u8isIDNoUse = TRUE;
624 }
625
626 if(u8isIDNoUse == TRUE)
627 IDs[u8MiuSel][u32index0] = 0;
628 }
629
630 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
631 {
632 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, (u8MiuSel== E_MIU_1), IDs[u8MiuSel][u32index0]);
633 }
634
635 return TRUE;
636 }
637
638 ////////////////////////////////////////////////////////////////////////////////
639 /// @brief \b Function \b Name: HAL_MIU_GetDefaultClientID_KernelProtect()
640 /// @brief \b Function \b Description: Get default client id array pointer for protect kernel
641 /// @param <RET> \b : The pointer of Array of client IDs
642 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetDefaultClientID_KernelProtect()643 MS_U8* HAL_MIU_GetDefaultClientID_KernelProtect()
644 {
645 if(IDNUM_KERNELPROTECT > 0)
646 return (MS_U8 *)&clientId_KernelProtect[0];
647
648 return NULL;
649 }
650
651 ////////////////////////////////////////////////////////////////////////////////
652 /// @brief \b Function \b Name: HAL_MIU_ProtectAlign()
653 /// @brief \b Function \b Description: Get the page shift for MIU protect
654 /// @param <*u32PageShift>\b IN: Page shift
655 /// @param <RET> \b OUT: None
656 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectAlign(void)657 MS_U32 HAL_MIU_ProtectAlign(void)
658 {
659 MS_U32 u32PageShift;
660
661 u32PageShift = MIU_PAGE_SHIFT;
662 return u32PageShift;
663 }
664
665 ////////////////////////////////////////////////////////////////////////////////
666 /// @brief \b Function \b Name: HAL_MIU_Dram_Size()
667 /// @brief \b Function \b Description: Set up Dram size for MIU protect
668 /// @param MiuID \b IN : MIU ID
669 /// @param DramSize \b IN : Specified Dram size for MIU protect
670 /// @param <OUT> \b None :
671 /// @param <RET> \b None :
672 /// @param <GLOBAL> \b None :
673 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_Size(MS_U8 MiuID,MS_U8 DramSize)674 MS_BOOL HAL_MIU_Dram_Size(MS_U8 MiuID, MS_U8 DramSize)
675 {
676 MS_U32 u32RegAddr;
677
678 if(E_MIU_0 == (MIU_ID)MiuID)
679 {
680 u32RegAddr = MIU_PROTECT_DDR_SIZE;
681 switch (DramSize)
682 {
683 case E_MIU_DDR_32MB:
684 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
685 break;
686 case E_MIU_DDR_64MB:
687 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
688 break;
689 case E_MIU_DDR_128MB:
690 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
691 break;
692 case E_MIU_DDR_256MB:
693 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
694 break;
695 case E_MIU_DDR_512MB:
696 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
697 break;
698 case E_MIU_DDR_1024MB:
699 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
700 break;
701 case E_MIU_DDR_2048MB:
702 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
703 break;
704 default:
705 return FALSE;
706 }
707 }
708 else
709 {
710 return FALSE;
711 }
712 return TRUE;
713 }
714
715 ////////////////////////////////////////////////////////////////////////////////
716 /// @brief \b Function \b Name: HAL_MIU_Dram_ReadSize()
717 /// @brief \b Function \b Description: Set up Dram size for MIU protect
718 /// @param MiuID \b IN : MIU ID
719 /// @param DramSize \b IN : Specified Dram size for MIU protect
720 /// @param <OUT> \b None :
721 /// @param <RET> \b None :
722 /// @param <GLOBAL> \b None :
723 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_ReadSize(MS_U8 MiuID,MIU_DDR_SIZE * pDramSize)724 MS_BOOL HAL_MIU_Dram_ReadSize(MS_U8 MiuID, MIU_DDR_SIZE *pDramSize)
725 {
726 return FALSE;
727 }
728
729 ////////////////////////////////////////////////////////////////////////////////
730 /// @brief \b Function \b Name: MDrv_MIU_GetClinetNumber()
731 /// @brief \b Function \b Description: Get the number of clients for specific MIU block
732 /// @param DramSize \b IN : MIU Block to protect (0 ~ 3)
733 /// @param <OUT> \b None :
734 /// @param <RET> \b None :
735 /// @param <GLOBAL> \b None :
736 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ClinetNumber(MS_U8 u8Blockx)737 MS_U8 HAL_MIU_ClinetNumber(MS_U8 u8Blockx)
738 {
739 MS_U8 u8ClientNumber;
740
741 switch (u8Blockx)
742 {
743 case E_MIU_BLOCK_0:
744 u8ClientNumber = MIU_BLOCK0_CLIENT_NUMBER;
745 break;
746 case E_MIU_BLOCK_1:
747 u8ClientNumber = MIU_BLOCK1_CLIENT_NUMBER;
748 break;
749 case E_MIU_BLOCK_2:
750 u8ClientNumber = MIU_BLOCK2_CLIENT_NUMBER;
751 break;
752 case E_MIU_BLOCK_3:
753 u8ClientNumber = MIU_BLOCK3_CLIENT_NUMBER;
754 break;
755 default:
756 u8ClientNumber = 0;
757 }
758
759 return u8ClientNumber;
760 }
761
762 ////////////////////////////////////////////////////////////////////////////////
763 /// @brief \b Function \b Name: HAL_MIU_Protect()
764 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
765 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
766 /// @param *pu8ProtectId \b IN : Allow specified client IDs to write
767 /// @param u32Start \b IN : Starting address
768 /// @param u32End \b IN : End address
769 /// @param bSetFlag \b IN : Disable or Enable MIU protection
770 /// - -Disable(0)
771 /// - -Enable(1)
772 /// @param <OUT> \b None :
773 /// @param <RET> \b None :
774 /// @param <GLOBAL> \b None :
775 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Protect(MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_PHY u32Start,MS_PHY u32End,MS_BOOL bSetFlag)776 MS_BOOL HAL_MIU_Protect(
777 MS_U8 u8Blockx,
778 MS_U8 *pu8ProtectId,
779 MS_PHY u32Start,
780 MS_PHY u32End,
781 MS_BOOL bSetFlag
782 )
783 {
784 MS_U32 u32RegAddr;
785 MS_U32 u32RegAddrStar;
786 MS_U32 u32RegAddrMSB;
787 MS_U32 u32RegAddrIDenable;
788 MS_U32 u32MiuProtectEn;
789 MS_U32 u32Reg;
790 MS_U16 u16Data;
791 MS_U16 u16Data1;
792 MS_U8 u8Data;
793 MS_U8 u8MiuSel;
794
795 u8MiuSel = E_MIU_0;
796 // Incorrect Block ID
797 if(u8Blockx > 3)
798 {
799 MIU_HAL_ERR("Err: Out of the number of protect device\n")
800 return false;
801 }
802 else if(((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0))
803 {
804 MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n")
805 return false;
806 }
807 else if(u32Start >= u32End)
808 {
809 MIU_HAL_ERR("Err: Start address is equal to or more than end address\n")
810 return false;
811 }
812
813 //write_enable
814 u8Data = 1 << u8Blockx;
815
816 // if( u32Start < HAL_MIU1_BASE)
817 {
818 u32MiuProtectEn = MIU_PROTECT_EN;
819 u32Reg = MIU_REG_BASE;
820
821 switch (u8Blockx)
822 {
823 case E_MIU_BLOCK_0:
824 u32RegAddr = MIU_PROTECT0_ID0;
825 u32RegAddrMSB = MIU_PROTECT0_MSB;
826 u32RegAddrStar = MIU_PROTECT0_START;
827 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
828 break;
829 case E_MIU_BLOCK_1:
830 u32RegAddr = MIU_PROTECT0_ID0;
831 u32RegAddrMSB = MIU_PROTECT1_MSB;
832 u32RegAddrStar = MIU_PROTECT1_START;
833 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
834 break;
835 case E_MIU_BLOCK_2:
836 u32RegAddr = MIU_PROTECT0_ID0;
837 u32RegAddrMSB = MIU_PROTECT2_MSB;
838 u32RegAddrStar = MIU_PROTECT2_START;
839 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
840 break;
841 case E_MIU_BLOCK_3:
842 u32RegAddr = MIU_PROTECT0_ID0;
843 u32RegAddrMSB = MIU_PROTECT3_MSB;
844 u32RegAddrStar = MIU_PROTECT3_START;
845 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
846 break;
847 default:
848 return false;
849 }
850 }
851
852 // Disable MIU protect
853 HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data,DISABLE);
854
855 if ( bSetFlag )
856 {
857 // Set Protect IDs
858 if(HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable) == FALSE)
859 {
860 return FALSE;
861 }
862
863 // Set BIT29,30 of start/end address
864 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
865 u16Data1 &= ~(0x0003 << (u8Blockx * 4));
866 u16Data1 |= (MS_U16)((u32Start >> 29) << (u8Blockx * 4));
867 u16Data1 &= ~(0x0003 << (u8Blockx * 4 + 2));
868 u16Data1 |= (MS_U16)(((u32End -1) >> 29) << (u8Blockx * 4 + 2));
869 HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1);
870
871 // Start Address
872 u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); //8k/unit
873 HAL_MIU_Write2Byte(u32RegAddrStar , u16Data);
874
875 // End Address
876 u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); //8k/unit;
877 HAL_MIU_Write2Byte(u32RegAddrStar + 2, u16Data);
878
879 // Enable MIU protect
880 HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE);
881 }
882 else
883 {
884 // Reset Protect IDs
885 HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable);
886 }
887
888 // clear log
889 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
890 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
891
892 return TRUE;
893 }
894
895 ////////////////////////////////////////////////////////////////////////////////
896 /// @brief \b Function \b Name: HAL_MIU_ProtectEx()
897 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
898 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
899 /// @param *pu8ProtectId \b IN : Allow specified client IDs to write
900 /// @param u32Start \b IN : Starting address
901 /// @param u32End \b IN : End address
902 /// @param bSetFlag \b IN : Disable or Enable MIU protection
903 /// - -Disable(0)
904 /// - -Enable(1)
905 /// @param <OUT> \b None :
906 /// @param <RET> \b None :
907 /// @param <GLOBAL> \b None :
908 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectEx(MS_U8 u8Blockx,MS_U32 * pu32ProtectId,MS_PHY u32Start,MS_PHY u32End,MS_BOOL bSetFlag)909 MS_BOOL HAL_MIU_ProtectEx(
910 MS_U8 u8Blockx,
911 MS_U32 *pu32ProtectId,
912 MS_PHY u32Start,
913 MS_PHY u32End,
914 MS_BOOL bSetFlag
915 )
916 {
917 return FALSE;
918 }
919
920 #define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO)
921 #define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID)
922
HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev,MIU_PortectInfo * pInfo)923 MS_BOOL HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev, MIU_PortectInfo *pInfo)
924 {
925 MS_U16 ret = 0;
926 MS_U16 loaddr = 0;
927 MS_U16 hiaddr = 0;
928 MS_U32 u32Address = 0;
929 MS_U32 u32Reg = (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE;
930
931 if (MIU_MAX_DEVICE <= u8MiuDev)
932 return FALSE;
933
934 if (!pInfo)
935 return FALSE;
936
937 ret = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_STATUS);
938 loaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_LOADDR);
939 hiaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_HIADDR);
940
941 pInfo->bHit = false;
942
943 if (REG_MIU_PROTECT_HIT_FALG & ret)
944 {
945 pInfo->bHit = TRUE;
946
947 pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(ret);
948 pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(ret) >> 4);
949 pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(ret) & 0x0F);
950 u32Address = (MS_U32)((hiaddr << 16) | loaddr) ;
951 u32Address = u32Address * MIU_PROTECT_ADDRESS_UNIT;
952
953 printf("MIU%u Block:%u Group:%u ClientID:%u Hitted_Address:0x%x<->0x%x\n", u8MiuDev, pInfo->u8Block, pInfo->u8Group, pInfo->u8ClientID, (unsigned int)u32Address, (unsigned int)(u32Address + MIU_PROTECT_ADDRESS_UNIT - 1));
954
955 //clear log
956 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
957 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
958 }
959
960 return TRUE;
961 }
962
963 ////////////////////////////////////////////////////////////////////////////////
964 /// @brief \b Function \b Name: HAL_MIU_SetSsc()
965 /// @brief \b Function \b Description: MDrv_MIU_SetSsc, @Step & Span
966 /// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40)
967 /// @param u16FDeviation \b IN : under 0.1% ~ 2% (Input Value = 1 ~ 20)
968 /// @param bEnable \b IN :
969 /// @param None \b OUT :
970 /// @param None \b RET :
971 /// @param None \b GLOBAL :
972 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetSsc(MS_U8 u8MiuDev,MS_U16 u16Fmodulation,MS_U16 u16FDeviation,MS_BOOL bEnable)973 MS_BOOL HAL_MIU_SetSsc(MS_U8 u8MiuDev, MS_U16 u16Fmodulation, MS_U16 u16FDeviation, MS_BOOL bEnable)
974 {
975 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE;
976 MS_U16 u16DDFSpan;
977 MS_U16 u16Input_DIV_First,u16Input_DIV_Second,u16Loop_DIV_First,u16Loop_DIV_Second;
978 MS_U8 u8Temp,i;
979
980 if (MIU_MAX_DEVICE <= u8MiuDev)
981 return FALSE;
982
983 //Pre check the input
984 if (u8MiuDev == 1)
985 {
986 if((HAL_MIU_Read2Byte(MIU1_REG_BASE)&BIT15))
987 {
988 uRegBase = MIU_ATOP_BASE+0x80;
989 }
990 else
991 {
992 printf("there is no MIU1\n");
993 return 0;
994 }
995 }
996 else
997 {
998 uRegBase = MIU_ATOP_BASE;
999 }
1000
1001 HAL_MIU_SSC_DBG(printf("MMIO base:%lx uRegBase:%lx\n", _gMIU_MapBase, uRegBase));
1002
1003 if ((u16Fmodulation<20)||(u16Fmodulation>40))
1004 {
1005 MIU_HAL_ERR("SSC u16Fmodulation Error...(20KHz - 40KHz)\n");
1006 return 0;
1007 }
1008
1009 if ((u16FDeviation<1)||(u16FDeviation>20))
1010 {
1011 MIU_HAL_ERR("SSC u16FDeviation Error...(0.1%% - 2%% ==> 1 ~20)\n");
1012 return 0;
1013 }
1014
1015 HAL_MIU_SSC_DBG(printf("---> u16Fmodulation = %d u16FDeviation = %d \n",(int)u16Fmodulation,(int)u16FDeviation));
1016 //<1>.Caculate DDFM = (Loop_DIV_First * Loop_DIV_Second)/(Input_DIV_First * Input_DIV_Second);
1017 //Prepare Input_DIV_First
1018 u8Temp = ((MS_U16)(HAL_MIU_Read2Byte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0x30)>>4); //Bit 13,12 (0x110D36)
1019 u16Input_DIV_First = 0x01;
1020 for (i=0;i<u8Temp;i++)
1021 u16Input_DIV_First = u16Input_DIV_First << 1;
1022 //Prepare Input_DIV_Second
1023 u16Input_DIV_Second = (HAL_MIU_ReadByte(uRegBase+MIU_PLL_INPUT_DIV_2ND)); //Bit 0~7 (0x101222)
1024 if (u16Input_DIV_Second == 0)
1025 u16Input_DIV_Second = 1;
1026 //Prepare Loop_DIV_First
1027 u8Temp = ((HAL_MIU_ReadByte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0xC0)>>6); //Bit 15,14 (0x110D36)
1028 u16Loop_DIV_First = 0x01;
1029 for (i=0;i<u8Temp;i++)
1030 u16Loop_DIV_First = u16Loop_DIV_First << 1;
1031
1032 //Prepare Loop_DIV_Second
1033 u16Loop_DIV_Second = (HAL_MIU_ReadByte(uRegBase+MIU_PLL_LOOP_DIV_2ND)); //Bit 0~7 (0x101223)
1034 if (u16Loop_DIV_Second == 0)
1035 u16Loop_DIV_Second = 1;
1036
1037 //<2>.From DDFSET register to get DDRPLL
1038 uDDFSET = HAL_MIU_Read4Byte(uRegBase+MIU_DDFSET) & 0x00ffffff;
1039 //DDRPLL = MPPL * DDR_FACTOR * Loop_First * Loop_Second / DDFSET * Input_First * Input_Second
1040 HAL_MIU_SSC_DBG(printf("---> Loop_First:%u Loop_Second:%u\n", u16Loop_DIV_First, u16Loop_DIV_Second));
1041 HAL_MIU_SSC_DBG(printf("---> Input_first:%u Input_second:%u\n", u16Input_DIV_First, u16Input_DIV_Second));
1042 uDDR_MHz = (MPPL * DDR_FACTOR * u16Loop_DIV_First * u16Loop_DIV_Second)/ (uDDFSET*u16Input_DIV_First*u16Input_DIV_Second);
1043 HAL_MIU_SSC_DBG(printf("---> uDDFSET = 0x%lx\n",uDDFSET));
1044 HAL_MIU_SSC_DBG(printf("---> DDR_MHZ = 0x%lx (%d MHz)\n",uDDR_MHz,(int)uDDR_MHz));
1045
1046 //<3>.Caculate DDFSPAN = (MPLL * DDFSPAN_FACTOR * MHz) / (DDFSET * Fmodulation * KHz)
1047 u16DDFSpan = (MS_U32)((DDFSPAN_FACTOR * MPPL/u16Fmodulation)* 1000/uDDFSET);
1048 HAL_MIU_SSC_DBG(printf("---> DDFSPAN = 0x%x (%d)\n",u16DDFSpan,(int)u16DDFSpan));
1049 if (u16DDFSpan > 0x3FFF)
1050 {
1051 u16DDFSpan = 0x3FFF;
1052 HAL_MIU_SSC_DBG(printf("??? DDFSPAN overflow > 0x3FFF, Fource set to 0x03FF\n"));
1053 }
1054
1055 //Write to Register
1056 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSPAN,u16DDFSpan);
1057 //<4>.Caculate DDFSTEP = (FDeviation*DDFSET/10)/(DDFSPAN*100)
1058 uDDFStep = (MS_U32)((u16FDeviation * (uDDFSET/10))/(u16DDFSpan*100));
1059 HAL_MIU_SSC_DBG(printf("---> DDFSTEP = 0x%lx (%lu)\n",uDDFStep,uDDFStep));
1060 //Write to Register
1061 uDDFStep &= (0x03FF);
1062 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSTEP,(HAL_MIU_Read2Byte(uRegBase+MIU_DDFSTEP) & (~0x03FF))|uDDFStep);
1063
1064 //<5>.Set ENABLE
1065 if(bEnable == ENABLE)
1066 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)|0xC0));
1067 else
1068 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)&(~0xC0))|0x80);
1069 return 1;
1070 }
1071
1072 ////////////////////////////////////////////////////////////////////////////////
1073 /// @brief \b Function \b Name: HAL_MIU_MaskReq()
1074 /// @brief \b Function \b Description: Mask MIU request
1075 /// @param u8Miu IN \b : miu0 or miu1
1076 /// @param eClientID IN \b : client ID
1077 /// @param None OUT \b :
1078 /// @param None RET \b :
1079 /// @param None GLOBAL \b :
1080 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_MaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1081 void HAL_MIU_MaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1082 {
1083 MS_S16 sVal;
1084 MS_U32 u32Reg;
1085
1086 if (MIU_MAX_DEVICE <= u8Miu)
1087 return;
1088
1089 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1090 if (sVal < 0)
1091 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1092 else
1093 {
1094 if(u8Miu == E_MIU_0)
1095 {
1096 MIU_RQX_MASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1097 }
1098 else if(u8Miu == E_MIU_1)
1099 {
1100 MIU1_RQX_MASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1101 }
1102 else
1103 {
1104 printf("%s not support MIU%u!\n", __FUNCTION__, u8Miu );
1105 return;
1106 }
1107
1108 HAL_MIU_Write2BytesBit(u32Reg, TRUE, BIT(MIU_GET_CLIENT_POS(sVal)));
1109 }
1110 }
1111
1112 ////////////////////////////////////////////////////////////////////////////////
1113 /// @brief \b Function \b Name: HAL_MIU_UnMaskReq()
1114 /// @brief \b Function \b Description: Mask MIU request
1115 /// @param u8Miu IN \b : miu0 or miu1
1116 /// @param eClientID IN \b : client ID
1117 /// @param None OUT \b :
1118 /// @param None RET \b :
1119 /// @param None GLOBAL \b :
1120 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_UnMaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1121 void HAL_MIU_UnMaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1122 {
1123 MS_S16 sVal;
1124 MS_U32 u32Reg;
1125
1126 if (MIU_MAX_DEVICE <= u8Miu)
1127 return;
1128
1129 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1130 if (sVal < 0)
1131 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1132 else
1133 {
1134 if(u8Miu == E_MIU_0)
1135 {
1136 MIU_RQX_MASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1137 }
1138 else if(u8Miu == E_MIU_1)
1139 {
1140 MIU1_RQX_MASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1141 }
1142 else
1143 {
1144 printf("%s not support MIU%u!\n", __FUNCTION__, u8Miu );
1145 return;
1146 }
1147
1148 HAL_MIU_Write2BytesBit(u32Reg, FALSE, BIT(MIU_GET_CLIENT_POS(sVal)));
1149 }
1150 }
1151
1152 ////////////////////////////////////////////////////////////////////////////////
1153 /// @brief \b Function \b Name: HAL_MIU_SelMIU()
1154 /// @brief \b Function \b Description: MIU selection
1155 /// @param u8MiuDev IN \b : miu device
1156 /// @param u16ClientID IN \b : client ID
1157 /// @param None OUT \b :
1158 /// @param None RET \b :
1159 /// @param None GLOBAL \b :
1160 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SelMIU(eMIU_SelType eType,eMIUClientID eClientID)1161 MS_BOOL HAL_MIU_SelMIU(eMIU_SelType eType, eMIUClientID eClientID)
1162 {
1163 MS_S16 sVal;
1164 MS_U32 u32Reg = 0;
1165
1166 //MIU 0
1167 sVal = HAL_MIU_GetClientInfo(0, eClientID);
1168 if (sVal < 0)
1169 goto fail;
1170
1171 u32Reg = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal));
1172 HAL_MIU_Write2BytesBit(u32Reg, (MIU_SELTYPE_MIU1 == eType), BIT(MIU_GET_CLIENT_POS(sVal)));
1173
1174 //MIU 1
1175 sVal = HAL_MIU_GetClientInfo(1, eClientID);
1176 if (sVal < 0)
1177 goto fail;
1178 u32Reg = MIU1_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal));
1179 HAL_MIU_Write2BytesBit(u32Reg, (MIU_SELTYPE_MIU_ALL == eType), BIT(MIU_GET_CLIENT_POS(sVal)));
1180
1181 return TRUE;
1182
1183 fail:
1184 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1185 return FALSE;
1186 }
1187
1188 ////////////////////////////////////////////////////////////////////////////////
1189 /// @brief \b Function \b Name: MDrv_MIU_Mask_Req_OPM_R()
1190 /// @brief \b Function \b Description: Set OPM MIU mask
1191 /// @param u8Mask IN \b : miu mask
1192 /// @param u8Miu IN \b : miu0 or miu1
1193 /// @param None OUT \b :
1194 /// @param None RET \b :
1195 /// @param None GLOBAL \b :
1196 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask,MS_U8 u8Miu)1197 void HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask, MS_U8 u8Miu)
1198 {
1199 if (MIU_MAX_DEVICE <= u8Miu)
1200 return;
1201
1202 if(u8Miu == 0)
1203 _MaskMiuReq_OPM_R(u8Mask);
1204 else
1205 _MaskMiu1Req_OPM_R(u8Mask);
1206
1207 }
1208
1209
1210 ////////////////////////////////////////////////////////////////////////////////
1211 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_R()
1212 /// @brief \b Function \b Description: Set OPM MIU mask
1213 /// @param u8Mask IN \b : miu mask
1214 /// @param u8Miu IN \b : miu0 or miu1
1215 /// @param None OUT \b :
1216 /// @param None RET \b :
1217 /// @param None GLOBAL \b :
1218 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask,MS_U8 u8Miu)1219 void HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask, MS_U8 u8Miu)
1220 {
1221 if (MIU_MAX_DEVICE <= u8Miu)
1222 return;
1223
1224 if (u8Miu == 0)
1225 _MaskMiuReq_DNRB_R(u8Mask);
1226 else
1227 _MaskMiu1Req_DNRB_R(u8Mask);
1228 }
1229
1230
1231 ////////////////////////////////////////////////////////////////////////////////
1232 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_W()
1233 /// @brief \b Function \b Description: Set OPM MIU mask
1234 /// @param u8Mask IN \b : miu mask
1235 /// @param u8Miu IN \b : miu0 or miu1
1236 /// @param None OUT \b :
1237 /// @param None RET \b :
1238 /// @param None GLOBAL \b :
1239 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask,MS_U8 u8Miu)1240 void HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask, MS_U8 u8Miu)
1241 {
1242 if (MIU_MAX_DEVICE <= u8Miu)
1243 return;
1244
1245 if (u8Miu == 0)
1246 _MaskMiuReq_DNRB_W(u8Mask);
1247 else
1248 _MaskMiu1Req_DNRB_W(u8Mask);
1249 }
1250
1251
1252 ////////////////////////////////////////////////////////////////////////////////
1253 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_RW()
1254 /// @brief \b Function \b Description: Set OPM MIU mask
1255 /// @param u8Mask IN \b : miu mask
1256 /// @param u8Miu IN \b : miu0 or miu1
1257 /// @param None OUT \b :
1258 /// @param None RET \b :
1259 /// @param None GLOBAL \b :
1260 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask,MS_U8 u8Miu)1261 void HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1262 {
1263 if (MIU_MAX_DEVICE <= u8Miu)
1264 return;
1265
1266 if (u8Miu == 0)
1267 _MaskMiuReq_DNRB_RW(u8Mask);
1268 else
1269 _MaskMiu1Req_DNRB_RW(u8Mask);
1270 }
1271
1272
1273 ////////////////////////////////////////////////////////////////////////////////
1274 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_SC_RW()
1275 /// @brief \b Function \b Description: Set OPM MIU mask
1276 /// @param u8Mask IN \b : miu mask
1277 /// @param u8Miu IN \b : miu0 or miu1
1278 /// @param None OUT \b :
1279 /// @param None RET \b :
1280 /// @param None GLOBAL \b :
1281 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask,MS_U8 u8Miu)1282 void HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1283 {
1284 if (MIU_MAX_DEVICE <= u8Miu)
1285 return;
1286
1287 if (u8Miu == 0)
1288 _MaskMiuReq_SC_RW(u8Mask);
1289 else
1290 _MaskMiu1Req_SC_RW(u8Mask);
1291 }
1292
1293
1294 ////////////////////////////////////////////////////////////////////////////////
1295 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVOP_R()
1296 /// @brief \b Function \b Description: Set OPM MIU mask
1297 /// @param u8Mask IN \b : miu mask
1298 /// @param u8Miu IN \b : miu0 or miu1
1299 /// @param None OUT \b :
1300 /// @param None RET \b :
1301 /// @param None GLOBAL \b :
1302 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask,MS_U8 u8Miu)1303 void HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask, MS_U8 u8Miu)
1304 {
1305 HAL_MIU_MaskReq(u8Miu, MIU_CLIENT_MVOP_64BIT_R);
1306 }
1307
1308 ////////////////////////////////////////////////////////////////////////////////
1309 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_R()
1310 /// @brief \b Function \b Description: Set OPM MIU mask
1311 /// @param u8Mask IN \b : miu mask
1312 /// @param u8Miu IN \b : miu0 or miu1
1313 /// @param None OUT \b :
1314 /// @param None RET \b :
1315 /// @param None GLOBAL \b :
1316 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask,MS_U8 u8Miu)1317 void HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask, MS_U8 u8Miu)
1318 {
1319 _FUNC_NOT_USED();
1320 }
1321
1322 ////////////////////////////////////////////////////////////////////////////////
1323 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_W()
1324 /// @brief \b Function \b Description: Set OPM MIU mask
1325 /// @param u8Mask IN \b : miu mask
1326 /// @param u8Miu IN \b : miu0 or miu1
1327 /// @param None OUT \b :
1328 /// @param None RET \b :
1329 /// @param None GLOBAL \b :
1330 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask,MS_U8 u8Miu)1331 void HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask, MS_U8 u8Miu)
1332 {
1333 _FUNC_NOT_USED();
1334 }
1335
1336
1337 ////////////////////////////////////////////////////////////////////////////////
1338 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_RW()
1339 /// @brief \b Function \b Description: Set OPM MIU mask
1340 /// @param u8Mask IN \b : miu mask
1341 /// @param u8Miu IN \b : miu0 or miu1
1342 /// @param None OUT \b :
1343 /// @param None RET \b :
1344 /// @param None GLOBAL \b :
1345 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask,MS_U8 u8Miu)1346 void HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1347 {
1348 HAL_MIU_MaskReq(u8Miu, MIU_CLIENT_MVD_RW);
1349 }
1350
1351
1352 ////////////////////////////////////////////////////////////////////////////////
1353 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_AUDIO_RW()
1354 /// @brief \b Function \b Description: Set OPM MIU mask
1355 /// @param u8Mask IN \b : miu mask
1356 /// @param u8Miu IN \b : miu0 or miu1
1357 /// @param None OUT \b :
1358 /// @param None RET \b :
1359 /// @param None GLOBAL \b :
1360 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask,MS_U8 u8Miu)1361 void HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1362 {
1363 if (MIU_MAX_DEVICE <= u8Miu)
1364 return;
1365
1366 if (u8Miu == 0)
1367 _MaskMiuReq_AUDIO_RW(u8Mask);
1368 else
1369 _MaskMiu1Req_AUDIO_RW(u8Mask);
1370
1371 }
1372
1373 ////////////////////////////////////////////////////////////////////////////////
1374 /// @brief \b Function \b Name: HAL_MIU_GET_MUX()
1375 /// @brief \b Function \b Description:
1376 /// @param None IN \b :
1377 /// @param None IN \b :
1378 /// @param None OUT \b :
1379 /// @param None RET \b :
1380 /// @param None GLOBAL \b :
1381 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GET_MUX(void)1382 MS_U16 HAL_MIU_GET_MUX(void)
1383 {
1384 return 0x0000;
1385 }
1386
1387 ////////////////////////////////////////////////////////////////////////////////
1388 /// @brief \b Function \b Name: HAL_MIU_SwitchMIU()
1389 /// @brief \b Function \b Description:
1390 /// @param u8MiuID \b IN : select MIU0 or MIU1
1391 /// @param None \b RET:
1392 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)1393 void HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)
1394 {
1395 HAL_MIU_SelMIU((eMIU_SelType)u8MiuID, MIU_CLIENT_MVOP_64BIT_R);
1396 }
1397
1398 ////////////////////////////////////////////////////////////////////////////////
1399 /// @brief \b Function \b Name: HAL_MIU_IsI64Mode()
1400 /// @brief \b Function \b Description:
1401 /// @param None \b RET: 0: not support, 64 or 128 bits
1402 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsI64Mode(void)1403 MS_U16 HAL_MIU_IsI64Mode(void)
1404 {
1405 return (HAL_MIU_ReadByte(MIU_REG_BASE+0x04) & REG_MIU_I64_MODE) ? (64) : (128);
1406 }
1407
1408 ////////////////////////////////////////////////////////////////////////////////
1409 /// @brief \b Function \b Name: HAL_MIU_IsInitMiu1()
1410 /// @brief \b Function \b Description:
1411 /// @param None \b RET:
1412 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsInitMiu1(void)1413 MS_BOOL HAL_MIU_IsInitMiu1(void)
1414 {
1415 return (HAL_MIU_Read2Byte(MIU1_REG_BASE) & REG_MIU_INIT_DONE) ? TRUE : FALSE;
1416 }
1417
1418 ////////////////////////////////////////////////////////////////////////////////
1419 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
1420 /// @brief \b Function \b Description: This function for set each group priority
1421 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1422 /// @param sPriority \b IN : gropu priority
1423 /// @param None \b RET: 0: Fail 1: Ok
1424 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev,MIU_GroupPriority sPriority)1425 MS_BOOL HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev, MIU_GroupPriority sPriority)
1426 {
1427 MS_U8 u8Val = 0;
1428 MS_U32 u32RegAddr = REG_MIU_GROUP_PRIORITY;
1429
1430 if (MIU_MAX_DEVICE <= u8MiuDev)
1431 return FALSE;
1432
1433 u8Val = (sPriority.u84th << 6 | sPriority.u83rd << 4 | sPriority.u82nd << 2 | sPriority.u81st);
1434 printf("Change miu%u group priority:%x\n", u8MiuDev, u8Val);
1435
1436 u32RegAddr += (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE;
1437 HAL_MIU_Write2BytesBit(u32RegAddr,DISABLE, BIT8);
1438 HAL_MIU_WriteByte(u32RegAddr, u8Val);
1439 HAL_MIU_Write2BytesBit(u32RegAddr,ENABLE, BIT8);
1440 return TRUE;
1441 }
1442
1443 ////////////////////////////////////////////////////////////////////////////////
1444 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
1445 /// @brief \b Function \b Description: This function for set each group priority
1446 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1447 /// @param eClientID \b IN : client ID
1448 /// @param bMask \b IN : TRUE: Mask high priority FALSE: Unmask hih priority
1449 /// @param None \b RET: 0: Fail 1: Ok
1450 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev,eMIUClientID eClientID,MS_BOOL bMask)1451 MS_BOOL HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev, eMIUClientID eClientID, MS_BOOL bMask)
1452 {
1453 MS_S16 sVal;
1454 MS_U32 u32Reg;
1455
1456 if (MIU_MAX_DEVICE <= u8MiuDev)
1457 return FALSE;
1458
1459 sVal = HAL_MIU_GetClientInfo(u8MiuDev, eClientID);
1460 if (sVal < 0)
1461 {
1462 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1463 return FALSE;
1464 }
1465 else
1466 {
1467 if(u8MiuDev == E_MIU_0)
1468 {
1469 MIU_RQX_HPMASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1470 }
1471 else if(u8MiuDev == E_MIU_1)
1472 {
1473 MIU1_RQX_HPMASK(u32Reg, MIU_GET_CLIENT_GROUP(sVal));
1474 }
1475 else
1476 {
1477 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
1478 return FALSE;
1479 }
1480
1481 HAL_MIU_Write2BytesBit(u32Reg, bMask, BIT(MIU_GET_CLIENT_POS(sVal)));
1482 }
1483 return TRUE;
1484 }
1485
HAL_MIU_GetAutoPhaseResult(MS_U32 * miu0,MS_U32 * miu1)1486 MS_BOOL HAL_MIU_GetAutoPhaseResult(MS_U32 *miu0, MS_U32 *miu1)
1487 {
1488 static MS_U32 u32Miu0 = 0, u32Miu1 = 0;
1489
1490 if (!u32Miu0)
1491 {
1492 u32Miu0 = HAL_MIU_Read4Byte(0x3390); //miu0 result
1493 u32Miu1 = HAL_MIU_Read4Byte(0x3394); //miu1 result
1494 *miu0 = u32Miu0;
1495 *miu1 = u32Miu1;
1496 }
1497 else
1498 {
1499 *miu0 = u32Miu0;
1500 *miu1 = u32Miu1;
1501 }
1502 return TRUE;
1503 }
1504
HAL_MIU_EnableScramble(MS_BOOL bEnable)1505 MS_BOOL HAL_MIU_EnableScramble(MS_BOOL bEnable)
1506 {
1507 return FALSE; // not implemented yet
1508 }
1509
HAL_MIU_IsScrambleEnabled(void)1510 MS_BOOL HAL_MIU_IsScrambleEnabled(void)
1511 {
1512 return FALSE; // not implemented yet
1513 }
1514
1515 ////////////////////////////////////////////////////////////////////////////////
1516 /// @brief \b Function \b Name: HAL_MIU_SetLoadingRequest
1517 /// @brief \b Function \b Description: Set loading request
1518 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1519 /// @return \b 0: Fail 1: OK
1520 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)1521 MS_BOOL HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)
1522 {
1523 MS_U32 u32RegAddr;
1524
1525 if (MIU_MAX_DEVICE <= u8MiuDev)
1526 return FALSE;
1527
1528 if (u8MiuDev == 1)
1529 {
1530 u32RegAddr = MIU1_BW_REQUEST;
1531 }
1532 else
1533 {
1534 u32RegAddr = MIU_BW_REQUEST;
1535 }
1536
1537 HAL_MIU_Write2Byte(u32RegAddr, 0x0050);
1538 HAL_MIU_Write2Byte(u32RegAddr, 0x0051);
1539
1540 return TRUE;
1541 }
1542
1543 ////////////////////////////////////////////////////////////////////////////////
1544 /// @brief \b Function \b Name: HAL_MIU_GetLoadingRequest
1545 /// @brief \b Function \b Description: Get loading request
1546 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1547 /// @param *u32Loading \b IN : percentage of MIU loading
1548 /// @return \b 0: Fail 1: OK
1549 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev,MS_U32 * u32Loading)1550 MS_BOOL HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev, MS_U32 *u32Loading)
1551 {
1552 MS_U16 u16Reg;
1553 MS_U32 u32RegAddr;
1554
1555 if (MIU_MAX_DEVICE <= u8MiuDev)
1556 return FALSE;
1557
1558 if (u8MiuDev == 1)
1559 {
1560 u32RegAddr = MIU1_BW_RESULT;
1561 }
1562 else
1563 {
1564 u32RegAddr = MIU_BW_RESULT;
1565 }
1566
1567 u16Reg = HAL_MIU_Read2Byte(u32RegAddr);
1568 *u32Loading =(MS_U32)((float)u16Reg * 100 / 0x400);
1569
1570 printf("MIU%d loading: %d%%\n", u8MiuDev, (int)(*u32Loading));
1571
1572 return TRUE;
1573 }
1574
1575 ////////////////////////////////////////////////////////////////////////////////
1576 /// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource
1577 /// @brief \b Function \b Description: Parse occupied resource to software structure
1578 /// @return \b 0: Fail 1: OK
1579 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ParseOccupiedResource(void)1580 MS_BOOL HAL_MIU_ParseOccupiedResource(void)
1581 {
1582 MS_U8 u8MiuSel;
1583 MS_U8 u8Blockx;
1584 MS_U8 u8ClientID;
1585 MS_U16 u16idenable;
1586 MS_U32 u32index;
1587 MS_U32 u32RegAddr;
1588 MS_U32 u32RegAddrIDenable;
1589
1590 for(u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++)
1591 {
1592 for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
1593 {
1594 if(u8MiuSel == E_MIU_0)
1595 {
1596 u32RegAddr = MIU_PROTECT0_ID0;
1597
1598 switch (u8Blockx)
1599 {
1600 case E_MIU_BLOCK_0:
1601 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
1602 break;
1603 case E_MIU_BLOCK_1:
1604 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
1605 break;
1606 case E_MIU_BLOCK_2:
1607 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
1608 break;
1609 case E_MIU_BLOCK_3:
1610 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
1611 break;
1612 default:
1613 return false;
1614 }
1615 }// if(u8MiuSel == E_MIU_0)
1616 else
1617 {
1618 u32RegAddr = MIU1_PROTECT0_ID0;
1619
1620 switch (u8Blockx)
1621 {
1622 case E_MIU_BLOCK_0:
1623 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
1624 break;
1625 case E_MIU_BLOCK_1:
1626 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
1627 break;
1628 case E_MIU_BLOCK_2:
1629 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
1630 break;
1631 case E_MIU_BLOCK_3:
1632 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
1633 break;
1634 default:
1635 return false;
1636 }
1637 }// if(u8MiuSel == E_MIU_0)
1638
1639 u16idenable = HAL_MIU_Read2Byte(u32RegAddrIDenable);
1640 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
1641 {
1642 IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16idenable >> u32index) & 0x1)? 1: 0;
1643 }
1644 }//for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
1645
1646 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
1647 {
1648 u8ClientID = HAL_MIU_ReadByte(u32RegAddr + u32index);
1649 IDs[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID];
1650 }
1651 }//for(u8MiuSel = E_MIU_0; u8MiuSel < E_MIU_NUM; u8MiuSel++)
1652
1653 return TRUE;
1654 }
1655
1656
HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)1657 void HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)
1658 {
1659
1660 MS_U16 val_16,val1_16,val2_16;
1661 MS_U32 val_32;
1662 MS_U32 u32RegAddrMSB;
1663 MS_U32 u32RegAddrStar;
1664
1665 if (MIU_MAX_DEVICE <= miu_dev)
1666 return;
1667
1668 if( miu_dev == 0 )
1669 {
1670 u32RegAddrMSB = MIU_PROTECT0_MSB;
1671 switch (u8Blockx)
1672 {
1673 case 0:
1674 u32RegAddrStar = MIU_PROTECT0_START;
1675 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1676 val1_16 = ( val1_16 & 0x1 );
1677 val2_16 = ( val1_16 & 0xC );
1678 break;
1679
1680 case 1:
1681 u32RegAddrStar = MIU_PROTECT1_START;
1682 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1683 val1_16 = ( val1_16 & 0x10 );
1684 val2_16 = ( val1_16 & 0xC0 );
1685 break;
1686
1687 case 2:
1688 u32RegAddrStar = MIU_PROTECT2_START;
1689 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1690 val1_16 = ( val1_16 & 0x100 );
1691 val2_16 = ( val1_16 & 0xC00 );
1692 break;
1693
1694 case 3:
1695 u32RegAddrStar = MIU_PROTECT3_START;
1696 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1697 val1_16 = ( val1_16 & 0x1000 );
1698 val2_16 = ( val1_16 & 0xC000 );
1699 break;
1700
1701 default:
1702 printf("error miu protect block number\n");
1703 return ;
1704 }
1705
1706 //protect start address
1707 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar);
1708 val_32 = ( ( val_16 ) | (( val1_16 ) << 4 )) << MIU_PAGE_SHIFT;
1709 printf("miu0 protect%d startaddr is 0x%x\n",u8Blockx, (unsigned int)val_32);
1710
1711 //protect end address
1712 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar+0x2);
1713
1714 val_32 = ((( val_16 + 1 ) | (( val1_16 ) << 4 ) ) << MIU_PAGE_SHIFT ) - 1;
1715 printf("miu0 protect%d endaddr is 0x%x\n",u8Blockx, (unsigned int)val_32);
1716
1717 }
1718
1719
1720 if( miu_dev == 1 )
1721 {
1722 u32RegAddrMSB = MIU1_PROTECT0_MSB;
1723 switch (u8Blockx)
1724 {
1725 case 0:
1726 u32RegAddrStar = MIU1_PROTECT0_START;
1727 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1728 val1_16 = ( val1_16 & 0x1 );
1729 val2_16 = ( val1_16 & 0xC );
1730 break;
1731
1732 case 1:
1733 u32RegAddrStar = MIU1_PROTECT1_START;
1734 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1735 val1_16 = ( val1_16 & 0x10 );
1736 val2_16 = ( val1_16 & 0xC0 );
1737 break;
1738
1739 case 2:
1740 u32RegAddrStar = MIU1_PROTECT2_START;
1741 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1742 val1_16 = ( val1_16 & 0x100 );
1743 val2_16 = ( val1_16 & 0xC00 );
1744 break;
1745
1746 case 3:
1747 u32RegAddrStar = MIU1_PROTECT3_START;
1748 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1749 val1_16 = ( val1_16 & 0x1000 );
1750 val2_16 = ( val1_16 & 0xC000 );
1751 break;
1752
1753 default:
1754 printf("error miu protect block number\n");
1755 return ;
1756 }
1757
1758 //protect start address
1759 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar);
1760 val_32 = ( ( val_16 ) | (( val1_16 ) << 4 )) << MIU_PAGE_SHIFT;
1761 printf("miu1 protect%d startaddr is 0x%x\n",u8Blockx, (unsigned int)val_32);
1762
1763 //protect end address
1764 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar+0x2);
1765
1766 val_32 = ((( val_16 + 1 ) | (( val1_16 ) << 4 ) ) << MIU_PAGE_SHIFT ) - 1;
1767 printf("miu1 protect%d endaddr is 0x%x\n",u8Blockx, (unsigned int)val_32);
1768
1769 }
1770
1771
1772 }
1773
HAL_MIU_PrintMIUProtectInfo(void)1774 void HAL_MIU_PrintMIUProtectInfo(void)
1775 {
1776 MS_U32 u32MiuProtectEn;
1777 MS_U32 u32MiuProtectIdEn;
1778
1779 MS_U8 val_8;
1780 MS_U16 val_16;
1781
1782 u32MiuProtectEn = MIU_PROTECT_EN;
1783
1784 u32MiuProtectIdEn= MIU_PROTECT0_ID_ENABLE;
1785
1786 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
1787
1788 //printf("val=%d\n",val);
1789
1790 if ( (val_8 & 0xf) != 0 )
1791 {
1792 printf("miu0 protect is enabled\n");
1793
1794 //protect_ID_enable information
1795 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1796 if ( val_16 != 0 )
1797 {
1798 printf("miu0 protect0_ID_enable is 0x%x\n",val_16);
1799 HAL_MIU_PrintMIUProtectArea(0,0);
1800 }
1801
1802 u32MiuProtectIdEn= MIU_PROTECT1_ID_ENABLE;
1803 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1804 if ( val_16 != 0 )
1805 {
1806 printf("miu0 protect1_ID_enable is 0x%x\n",val_16);
1807 HAL_MIU_PrintMIUProtectArea(1,0);
1808 }
1809
1810 u32MiuProtectIdEn= MIU_PROTECT2_ID_ENABLE;
1811 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1812 if ( val_16 != 0 )
1813 {
1814 printf("miu0 protect2_ID_enable is 0x%x\n",val_16);
1815 HAL_MIU_PrintMIUProtectArea(2,0);
1816 }
1817
1818 u32MiuProtectIdEn= MIU_PROTECT3_ID_ENABLE;
1819 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1820 if ( val_16 != 0 )
1821 {
1822 printf("miu0 protect3_ID_enable is 0x%x\n",val_16);
1823 HAL_MIU_PrintMIUProtectArea(3,0);
1824 }
1825
1826 }
1827 else
1828 {
1829 printf("miu0 protect is not enabled\n");
1830 }
1831
1832 u32MiuProtectEn=MIU1_PROTECT_EN;
1833
1834 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
1835
1836 //printf("val=%d\n",val);
1837
1838 if ( (val_8 & 0xf) != 0x0 )
1839 {
1840 printf("miu1 protect is enabled\n");
1841
1842 //protect_ID_enable information
1843 u32MiuProtectIdEn= MIU1_PROTECT0_ID_ENABLE;
1844 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1845 if ( val_16 != 0 )
1846 {
1847 printf("miu1 protect0_ID_enable is 0x%x\n",val_16);
1848 HAL_MIU_PrintMIUProtectArea(0,1);
1849 }
1850
1851 u32MiuProtectIdEn= MIU1_PROTECT1_ID_ENABLE;
1852 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1853 if ( val_16 != 0 )
1854 {
1855 printf("miu1 protect1_ID_enable is 0x%x\n",val_16);
1856 HAL_MIU_PrintMIUProtectArea(1,1);
1857 }
1858
1859 u32MiuProtectIdEn= MIU1_PROTECT2_ID_ENABLE;
1860 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1861 if ( val_16 != 0 )
1862 {
1863 printf("miu1 protect2_ID_enable is 0x%x\n",val_16);
1864 HAL_MIU_PrintMIUProtectArea(2,1);
1865 }
1866
1867 u32MiuProtectIdEn= MIU1_PROTECT3_ID_ENABLE;
1868 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
1869 if ( val_16 != 0 )
1870 {
1871 printf("miu1 protect3_ID_enable is 0x%x\n",val_16);
1872 HAL_MIU_PrintMIUProtectArea(3,1);
1873 }
1874
1875
1876 }
1877 else
1878 {
1879 printf("miu1 protect is not enabled\n");
1880
1881 }
1882 }
1883
1884 ////////////////////////////////////////////////////////////////////////////////
1885 /// @brief \b Function \b Name: HAL_MIU_GetClientWidth
1886 /// @brief \b Function \b Description: Get MIU client bus width
1887 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1888 /// @param eClientID \b IN : client ID
1889 /// @param pClientWidth \b IN : client bus width
1890 /// @return \b 0 : Fail 1: OK
1891 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi,eMIUClientID eClientID,eMIU_ClientWidth * pClientWidth)1892 MS_BOOL HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi, eMIUClientID eClientID, eMIU_ClientWidth *pClientWidth)
1893 {
1894 MS_U32 u32Reg;
1895 MS_S16 sVal;
1896 MS_U16 u16Group;
1897 MS_U16 u16Client;
1898 MS_U16 u16RegVal;
1899
1900 if (MIU_MAX_DEVICE <= u8MiuDevi)
1901 return FALSE;
1902
1903 sVal = HAL_MIU_GetClientInfo(u8MiuDevi, eClientID);
1904
1905 if (sVal < 0)
1906 {
1907 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1908 return FALSE;
1909 }
1910 else
1911 {
1912 u16Group = MIU_GET_CLIENT_GROUP(sVal);
1913 u16Client = MIU_GET_CLIENT_POS(sVal);
1914
1915 if(u16Group >= 3)
1916 {
1917 *pClientWidth = E_MIU_CLIENT_256BIT;
1918 return TRUE;
1919 }
1920
1921 u32Reg = REG_MI64_FORCE + (MIU_GET_CLIENT_GROUP(sVal) << 1);
1922 u16RegVal = HAL_MIU_Read2Byte(u32Reg);
1923
1924 if(u16RegVal & (1 << u16Client))
1925 *pClientWidth = E_MIU_CLIENT_64BIT;
1926 else
1927 *pClientWidth = E_MIU_CLIENT_128BIT;
1928
1929 return TRUE;
1930 }
1931 }
1932
1933
HAL_MIU_GetDramType(MS_U32 eMiu,MIU_DDR_TYPE * pType)1934 MS_BOOL HAL_MIU_GetDramType(MS_U32 eMiu, MIU_DDR_TYPE* pType)
1935 {
1936 MS_U32 u32Reg;
1937
1938 if (eMiu >= MIU_MAX_DEVICE)
1939 return FALSE;
1940
1941 switch (eMiu)
1942 {
1943 case 0:
1944 u32Reg = REG_MIU_DDR_STATUS;
1945 break;
1946 default:
1947 return FALSE;
1948 }
1949
1950 if (HAL_MIU_Read2Byte(u32Reg)& REG_MIU_DDR4)
1951 {
1952 *pType = E_MIU_DDR4;
1953 }
1954 else
1955 {
1956 *pType = E_MIU_DDR3;
1957 }
1958
1959 return TRUE;
1960 }
1961