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Searched refs:MAX_TASKS (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 2 // max tasks number macro
138 #define MAX_TASKS 2 // max tasks number macro
234 unsigned int heap_size[MAX_TASKS]; // CTL_INFO_ADDR + 0x18 heap size available for each task
239 unsigned int task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
241 unsigned short task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x44 0:normal 1:3d WMV 2:korea 3d TV
269 unsigned char STCindex[MAX_TASKS];
270 unsigned char STCMode[MAX_TASKS];
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/ !
H A Dcontroller.h133 #define MAX_TASKS 16 // max tasks number macro
369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning
387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/ !
H A Dcontroller.h127 #define MAX_TASKS 16 // max tasks number macro
271 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment
272 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV
273 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning