Searched refs:HW4_CFG37_MASK_SCR_PVR3_EN (Results 1 – 11 of 11) sorted by relevance
1838 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
1876 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
5643 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()5663 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()
1878 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
1958 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
1930 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
2007 #define HW4_CFG37_MASK_SCR_PVR3_EN 0x0800 macro
6158 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()6178 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()
5787 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()5807 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()