Searched refs:HW4_CFG37_MASK_SCR_PVR2_EN (Results 1 – 12 of 12) sorted by relevance
1837 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
4272 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()4286 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()
1875 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
5640 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()5660 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()
1877 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
1957 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
1929 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
2006 #define HW4_CFG37_MASK_SCR_PVR2_EN 0x0400 macro
6155 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()6175 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()
5784 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()5804 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()