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Searched refs:CPU_INT_REG (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
322 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
324 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H3; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H3); in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DhalMBXINT.c304 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
305 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
319 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
321 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
329 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
330 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DhalMBXINT.c303 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
304 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
318 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
319 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
327 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H2; in MHAL_MBXINT_Fire()
328 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H2); in MHAL_MBXINT_Fire()
341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
350 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H2); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DhalMBXINT.c310 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
311 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
330 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DhalMBXINT.c306 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
307 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
354 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
355 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DhalMBXINT.c303 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
304 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
318 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
319 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
327 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H2; in MHAL_MBXINT_Fire()
328 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H2); in MHAL_MBXINT_Fire()
341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
350 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H2); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DhalMBXINT.c306 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
307 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
354 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
355 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON; in MHAL_MBXINT_Fire()
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON); in MHAL_MBXINT_Fire()
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1; in MHAL_MBXINT_Fire()
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1); in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
[all …]

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