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Searched refs:BMASK (Results 1 – 25 of 496) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c247 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
269 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
474 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
475 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
479 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
480 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
484 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
485 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
489 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
490 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c227 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
249 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
402 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
403 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
407 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
408 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
412 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
413 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
417 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
418 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c247 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
269 if((R2BYTE(REG_HDMI2_DUAL_1_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux1()
291 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
313 if(R2BYTEMSK(REG_HDMI_DUAL_1_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect1()
540 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
541 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
545 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
546 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
550 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
551 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c247 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
269 if((R2BYTE(REG_HDMI2_DUAL_1_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux1()
291 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
313 if(R2BYTEMSK(REG_HDMI_DUAL_1_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect1()
540 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
541 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
545 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
546 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
550 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
551 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c253 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
275 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
481 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
482 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
486 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
487 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
491 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
492 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
496 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
497 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c253 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
275 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
481 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
482 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
486 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
487 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
491 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
492 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
496 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
497 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c234 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
256 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
410 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
415 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
416 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
420 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
421 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
425 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
426 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c234 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
256 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
410 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
415 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
416 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
420 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
421 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
425 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
426 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c230 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
252 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
410 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
415 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
416 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
420 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
421 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c230 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
252 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
410 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
415 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
416 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
420 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
421 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c230 if((R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)) == ucPortSelect) in _Hal_tmds_CheckPortSelectMux0()
252 if(R2BYTEMSK(REG_HDMI_DUAL_0_40_L, BMASK(6:5)) == 0x60) in _Hal_tmds_CheckYUV420PortSelect0()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
410 W2BYTEMSK(REG_PM_SCDC1_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC1_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
415 W2BYTEMSK(REG_PM_SCDC2_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
416 W2BYTEMSK(REG_PM_SCDC2_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
420 W2BYTEMSK(REG_PM_SCDC3_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
421 W2BYTEMSK(REG_PM_SCDC3_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c148 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
149 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
157 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
158 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
160 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
164 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
165 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c148 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
149 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
157 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
158 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
160 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
164 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
165 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/messi/pwm/
H A DhalPWM.c200 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
203 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
206 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
209 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
212 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0)); in HAL_PWM_Oen()
330 HAL_TOP_WriteRegBit(REG_PWM_MODE,BITS(2:2,1), BMASK(2:2)); in HAL_PWM_Oen()
333 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1)); in HAL_PWM_Oen()
334 HAL_TOP_WriteRegBit(REG_PWM_MODE,BITS(6:6,1), BMASK(6:6)); in HAL_PWM_Oen()
337 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2)); in HAL_PWM_Oen()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c142 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
143 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
151 …{REG_MHL_CBUS_59, BMASK(15:0), 0xADB0}, // timeout for a device receiving a packet within a command
152 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 110ms
154 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
158 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
159 {REG_MHL_CBUS_71, BMASK(15:14), BMASK(15:14)},
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c142 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
143 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
151 …{REG_MHL_CBUS_59, BMASK(15:0), 0xADB0}, // timeout for a device receiving a packet within a command
152 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 110ms
154 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
158 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
159 {REG_MHL_CBUS_71, BMASK(15:14), BMASK(15:14)},
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7621/pwm/
H A DhalPWM.c197 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
200 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
203 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
206 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
209 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
326 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0)); in HAL_PWM_Oen()
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1)); in HAL_PWM_Oen()
332 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2)); in HAL_PWM_Oen()
335 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3)); in HAL_PWM_Oen()
338 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4)); in HAL_PWM_Oen()
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/maserati/pwm/
H A DhalPWM.c197 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
200 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
203 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
206 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
209 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
326 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0)); in HAL_PWM_Oen()
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1)); in HAL_PWM_Oen()
332 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2)); in HAL_PWM_Oen()
335 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3)); in HAL_PWM_Oen()
338 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4)); in HAL_PWM_Oen()
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7821/pwm/
H A DhalPWM.c197 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
200 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
203 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
206 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
209 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
326 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0)); in HAL_PWM_Oen()
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1)); in HAL_PWM_Oen()
332 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2)); in HAL_PWM_Oen()
335 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3)); in HAL_PWM_Oen()
338 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4)); in HAL_PWM_Oen()
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/mooney/pwm/
H A DhalPWM.c197 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
200 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
203 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
206 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
209 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14)); in _HAL_PWM_VDBen_SW()
326 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0)); in HAL_PWM_Oen()
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1)); in HAL_PWM_Oen()
332 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2)); in HAL_PWM_Oen()
335 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3)); in HAL_PWM_Oen()
338 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4)); in HAL_PWM_Oen()
[all …]

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