Lines Matching refs:BMASK
148 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
149 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
157 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
158 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
160 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
164 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
165 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
169 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
170 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), 0},
205 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
213 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
221 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
410 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
415 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
421 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
433 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
437 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
438 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
444 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
456 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
457 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
460 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
461 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
467 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
479 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
480 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
483 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
484 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
490 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
524 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
525 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
528 … W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
529 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
530 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
531 W2BYTEMSK(REG_COMBO_PHY1_P0_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
536 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
548 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
549 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
552 … W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
553 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
554 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
555 W2BYTEMSK(REG_COMBO_PHY1_P1_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
560 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
572 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
573 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
576 … W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
577 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
578 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
579 W2BYTEMSK(REG_COMBO_PHY1_P2_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
596 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
597 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
600 … W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
601 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
602 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
603 W2BYTEMSK(REG_COMBO_PHY1_P3_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
608 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
707 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
712 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
717 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
731 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
736 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
741 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
779 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
784 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
789 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
1162 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4; in _mhal_mhl_ChangeScalerMainMux()
1168 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1175 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1227 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
1259 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2); in _mhal_mhl_GetEMSCOneByteCRC()
1292 …MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0))… in _mhal_mhl_GetEMSCTwoByteCRC()
1316 return (ucCommand &BMASK(7:0)); in _mhal_mhl_GetEMSCTwoByteCRC()
1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1452 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4)); in _mhal_mhl_ECbusInitialSetting()
1453 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1)); in _mhal_mhl_ECbusInitialSetting()
1454 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1455 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13] in _mhal_mhl_ECbusInitialSetting()
1458 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1459 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0] in _mhal_mhl_ECbusInitialSetting()
1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1463 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0)); in _mhal_mhl_ECbusInitialSetting()
1468 …W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_c… in _mhal_mhl_ECbusInitialSetting()
1471 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1472 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1473 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1474 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch in _mhal_mhl_ECbusInitialSetting()
1475 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1476 …W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa da… in _mhal_mhl_ECbusInitialSetting()
1479 …7, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4), BMASK(15:0)); // [15:8]:… in _mhal_mhl_ECbusInitialSetting()
1480 …8, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6), BMASK(15:0)); // [15:8]:… in _mhal_mhl_ECbusInitialSetting()
1481 …SCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 2) << 6), BMASK(8:6)| BMASK(5:3)); // [8… in _mhal_mhl_ECbusInitialSetting()
1486 …W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg… in _mhal_mhl_ECbusInitialSetting()
1487 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1488 …W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_w… in _mhal_mhl_ECbusInitialSetting()
1489 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1490 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); // in _mhal_mhl_ECbusInitialSetting()
1491 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); // in _mhal_mhl_ECbusInitialSetting()
1494 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1495 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1496 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
1500 …W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0… in _mhal_mhl_ECbusInitialSetting()
1501 …W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:re… in _mhal_mhl_ECbusInitialSetting()
1502 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
1503 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1504 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
1508 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x33, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1511 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1516 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1573 …W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0… in _mhal_mhl_CbusConnectCheckEnable()
1590 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1648 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1649 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1664 …W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_sho… in _mhal_mhl_SetShortReadAddress()
1687 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1688 …0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1699 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1700 …0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1711 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1712 …0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1723 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1724 …0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1784 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1814 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
1846 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1865 return (R2BYTE(REG_MHL_ECBUS_22) &BMASK(7:0)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1880 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0)); in _mhal_mhl_InsertSRAMSendEMSCData()
1907 if((usECbusData[ustemp] &BMASK(7:0)) == 0x39) // Find CBUS1_START in _mhal_mhl_ParsingECbusCommand()
1918 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0)); in _mhal_mhl_ParsingECbusCommand()
1930 msg_mhl(printf(" MHL [SK][MSC][C] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1934 msg_mhl(printf(" MHL [SK][MSC][D] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1938 msg_mhl(printf(" MHL [SK][DDC][C] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1942 msg_mhl(printf(" MHL [SK][DDC][D] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1946 msg_mhl(printf(" MHL [SK] unknow = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1960 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0)); in _mhal_mhl_ParsingECbusCommand()
1972 msg_mhl(printf(" MHL [SO][MSC][C] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1976 msg_mhl(printf(" MHL [SO][MSC][D] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1980 msg_mhl(printf(" MHL [SO][DDC][C] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1984 msg_mhl(printf(" MHL [SO][DDC][D] = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
1988 msg_mhl(printf(" MHL [SO] unknow = %x\r\n", (usValue &BMASK(7:0)))); in _mhal_mhl_ParsingECbusCommand()
2025 ucReceiveData = (R2BYTE(REG_MHL_ECBUS_7C) &BMASK(7:0)); in _mhal_mhl_GetECbusCommand()
2144 return (R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)); in mhal_mhl_GetInputPort()
2182 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0); in mhal_mhl_CheckPIPWindow()
2183 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0); in mhal_mhl_CheckPIPWindow()
2185 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4; in mhal_mhl_CheckPIPWindow()
2827 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2831 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2835 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2858 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2862 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2866 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2879 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2883 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2887 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2982 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
3083 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
3116 …W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en… in mhal_mhl_initial()
3250 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3254 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3290 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3294 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3320 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3324 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3632 … msg_mhl(printf(" MHL send MSG command = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0)))); in mhal_mhl_CBusWrite()
3636 msg_mhl(printf(" MHL send MSG data = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0)))); in mhal_mhl_CBusWrite()
3950 if((ustemp & BMASK(1:0)) == 0x03) in mhal_mhl_RtermControlHWMode()
4082 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4087 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4200 …W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4219 …W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4238 …W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4257 …W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4433 usEMSCFreeBuffer = (R2BYTE(REG_MHL_ECBUS_24) &BMASK(9:0)); // REG_MHL_ECBUS_24[9:0] in mhal_mhl_GetEMSCReceiveData()
4453 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0)); in mhal_mhl_GetEMSCReceiveData()
4474 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count in mhal_mhl_InsertEMSCSendData()
4475 …W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte c… in mhal_mhl_InsertEMSCSendData()
4477 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()