Lines Matching refs:BMASK
142 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
143 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
151 …{REG_MHL_CBUS_59, BMASK(15:0), 0xADB0}, // timeout for a device receiving a packet within a command
152 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 110ms
154 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
158 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
159 {REG_MHL_CBUS_71, BMASK(15:14), BMASK(15:14)},
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
163 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
164 {REG_MHL_CBUS_71, BMASK(15:14), 0},
199 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
207 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
215 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
397 W2BYTEMSK(REG_DVI_DTOP_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
405 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypa… in _mhal_mhl_HdmiBypassModeSetting()
407 …W2BYTEMSK(REG_DVI_ATOP_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrti… in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_DVI_DTOP_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
424 W2BYTEMSK(REG_DVI_DTOP1_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
425 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
430 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
431 …W2BYTEMSK(REG_DVI_ATOP1_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_HdmiBypassModeSetting()
435 …W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_DVI_DTOP1_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
451 W2BYTEMSK(REG_DVI_DTOP3_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
452 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
458 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
459 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
461 …W2BYTEMSK(REG_DVI_ATOP3_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
467 W2BYTEMSK(REG_DVI_DTOP3_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
478 …W2BYTEMSK(REG_DVI_DTOP2_27_L, 0x2C6C, BMASK(14:0)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode,… in _mhal_mhl_HdmiBypassModeSetting()
479 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
485 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
486 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
488 …W2BYTEMSK(REG_DVI_ATOP2_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
494 W2BYTEMSK(REG_DVI_DTOP2_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
527 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
538 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, E… in _mhal_mhl_Mhl24bitsModeSetting()
540 …W2BYTEMSK(REG_DVI_ATOP_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value… in _mhal_mhl_Mhl24bitsModeSetting()
545 W2BYTEMSK(REG_DVI_DTOP_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
556 W2BYTEMSK(REG_DVI_DTOP1_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
557 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
565 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
566 …W2BYTEMSK(REG_DVI_ATOP1_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_Mhl24bitsModeSetting()
568 …W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power d… in _mhal_mhl_Mhl24bitsModeSetting()
573 W2BYTEMSK(REG_DVI_DTOP1_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 …W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
585 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
594 …2BYTEMSK(REG_DVI_DTOP3_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
595 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
597 …W2BYTEMSK(REG_DVI_ATOP3_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL valu… in _mhal_mhl_Mhl24bitsModeSetting()
602 W2BYTEMSK(REG_DVI_DTOP3_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
613 …W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
614 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
623 …2BYTEMSK(REG_DVI_DTOP2_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
624 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
626 …W2BYTEMSK(REG_DVI_ATOP2_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
631 W2BYTEMSK(REG_DVI_DTOP2_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
664 W2BYTEMSK(REG_DVI_DTOP_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
665 W2BYTEMSK(REG_DVI_ATOP_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
676 W2BYTEMSK(REG_DVI_DTOP1_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
688 W2BYTEMSK(REG_DVI_DTOP3_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
689 W2BYTEMSK(REG_DVI_ATOP3_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
700 W2BYTEMSK(REG_DVI_DTOP2_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
734 W2BYTEMSK(REG_DVI_ATOP_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
739 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
744 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
782 W2BYTEMSK(REG_DVI_ATOP3_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
787 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
792 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
1189 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4; in _mhal_mhl_ChangeScalerMainMux()
1195 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1202 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
1377 return (R2BYTE(REG_DVI_ATOP_6A_L) &BMASK(1:0)); in mhal_mhl_GetInputPort()
1415 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0); in mhal_mhl_CheckPIPWindow()
1416 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0); in mhal_mhl_CheckPIPWindow()
1418 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4; in mhal_mhl_CheckPIPWindow()
2008 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2012 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2016 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2039 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2043 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2047 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2060 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2064 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2068 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2163 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
2264 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
2431 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2435 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2471 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2475 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2501 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2505 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3033 if((ustemp & BMASK(1:0)) == 0x03) in mhal_mhl_RtermControlHWMode()
3167 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
3172 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()