Lines Matching refs:BMASK
159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 …{REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
180 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
181 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), 0},
216 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
224 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
232 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
435 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
439 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
450 … W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
459 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
460 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
463 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
464 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
483 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
484 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
487 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
488 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
498 … W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
531 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
535 … W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
537 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
538 W2BYTEMSK(REG_COMBO_PHY1_P0_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
568 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
572 … W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
573 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
574 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
575 W2BYTEMSK(REG_COMBO_PHY1_P1_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
596 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
605 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
606 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
609 … W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
610 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
611 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
612 W2BYTEMSK(REG_COMBO_PHY1_P2_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
642 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
643 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
646 … W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
647 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
648 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
649 W2BYTEMSK(REG_COMBO_PHY1_P3_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
670 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
785 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
796 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
801 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
806 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
817 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
822 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
827 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
1067 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4; in _mhal_mhl_ChangeScalerMainMux()
1073 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1080 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1123 W2BYTEMSK(REG_COMBO_PHY0_P0_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1124 W2BYTEMSK(REG_COMBO_PHY1_P0_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1134 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1135 W2BYTEMSK(REG_COMBO_PHY0_P1_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1136 W2BYTEMSK(REG_COMBO_PHY1_P1_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1146 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1147 W2BYTEMSK(REG_COMBO_PHY0_P2_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1148 W2BYTEMSK(REG_COMBO_PHY1_P2_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1158 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1159 W2BYTEMSK(REG_COMBO_PHY0_P3_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1160 W2BYTEMSK(REG_COMBO_PHY1_P3_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
1205 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2); in _mhal_mhl_GetEMSCOneByteCRC()
1238 …MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0))… in _mhal_mhl_GetEMSCTwoByteCRC()
1262 return (ucCommand &BMASK(7:0)); in _mhal_mhl_GetEMSCTwoByteCRC()
1396 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1398 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4)); in _mhal_mhl_ECbusInitialSetting()
1399 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1)); in _mhal_mhl_ECbusInitialSetting()
1400 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1401 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1402 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1403 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13] in _mhal_mhl_ECbusInitialSetting()
1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1405 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0] in _mhal_mhl_ECbusInitialSetting()
1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1409 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0)); in _mhal_mhl_ECbusInitialSetting()
1414 …W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_c… in _mhal_mhl_ECbusInitialSetting()
1417 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1418 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1420 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch in _mhal_mhl_ECbusInitialSetting()
1421 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1422 …W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa da… in _mhal_mhl_ECbusInitialSetting()
1425 …7, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4), BMASK(15:0)); // [15:8]:… in _mhal_mhl_ECbusInitialSetting()
1426 …8, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6), BMASK(15:0)); // [15:8]:… in _mhal_mhl_ECbusInitialSetting()
1427 …CRC(1, 1) << 3)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 2) << 6), BIT(11)| BMASK(8:6)| BMASK(5:3)); // [8… in _mhal_mhl_ECbusInitialSetting()
1432 …W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg… in _mhal_mhl_ECbusInitialSetting()
1433 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1434 …W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_w… in _mhal_mhl_ECbusInitialSetting()
1435 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1436 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); // in _mhal_mhl_ECbusInitialSetting()
1437 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); // in _mhal_mhl_ECbusInitialSetting()
1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
1446 …W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0… in _mhal_mhl_ECbusInitialSetting()
1447 …W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:re… in _mhal_mhl_ECbusInitialSetting()
1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
1449 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
1454 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x22, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1462 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1519 …W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0… in _mhal_mhl_CbusConnectCheckEnable()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1571 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1581 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1587 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1604 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1654 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1655 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1670 …W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_sho… in _mhal_mhl_SetShortReadAddress()
1686 W2BYTEMSK(REG_MHL_ECBUS_0F, bEnableFlag? (BIT(8)| 0x4): 0, BIT(8)| BMASK(3:0)); in _mhal_mhl_ECbusStateOverwrite()
1705 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1706 …0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1707 …((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-contr… in _mhal_mhl_Version3PhyEnable()
1715 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1716 …0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1717 …((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-contr… in _mhal_mhl_Version3PhyEnable()
1725 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1726 …0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1727 …((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-contr… in _mhal_mhl_Version3PhyEnable()
1735 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1736 …0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channe… in _mhal_mhl_Version3PhyEnable()
1737 …((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-contr… in _mhal_mhl_Version3PhyEnable()
1766 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(12), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1770 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1777 W2BYTEMSK(REG_MHL_ECBUS_2E, bEnableFlag? BIT(12): BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
1859 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1878 return (R2BYTE(REG_MHL_ECBUS_22) &BMASK(7:0)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1893 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0)); in _mhal_mhl_InsertSRAMSendEMSCData()
1920 if((usECbusData[ustemp] &BMASK(7:0)) == 0x39) // Find CBUS1_START in _mhal_mhl_ParsingECbusCommand()
1931 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0)); in _mhal_mhl_ParsingECbusCommand()
1943 MHAL_MHL_MSG_DEBUG(" MHL [SK][MSC][C] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1947 MHAL_MHL_MSG_DEBUG(" MHL [SK][MSC][D] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1951 MHAL_MHL_MSG_DEBUG(" MHL [SK][DDC][C] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1955 MHAL_MHL_MSG_DEBUG(" MHL [SK][DDC][D] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1959 MHAL_MHL_MSG_DEBUG(" MHL [SK] unknow = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1973 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0)); in _mhal_mhl_ParsingECbusCommand()
1985 MHAL_MHL_MSG_DEBUG(" MHL [SO][MSC][C] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1989 MHAL_MHL_MSG_DEBUG(" MHL [SO][MSC][D] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1993 MHAL_MHL_MSG_DEBUG(" MHL [SO][DDC][C] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
1997 MHAL_MHL_MSG_DEBUG(" MHL [SO][DDC][D] = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
2001 MHAL_MHL_MSG_DEBUG(" MHL [SO] unknow = %x\r\n", (usValue &BMASK(7:0))); in _mhal_mhl_ParsingECbusCommand()
2084 …W2BYTEMSK(REG_MHL_ECBUS_7A, bEnableFlag? BIT(5)| BIT(4)| BMASK(3:0): 0, BIT(5)| BIT(4)| BMASK(3:0)… in _mhal_mhl_BISTECbusEnable()
2085 W2BYTEMSK(REG_MHL_ECBUS_06, bEnableFlag? 0x1800: 0x1C00, BMASK(14:8)); in _mhal_mhl_BISTECbusEnable()
2086 W2BYTEMSK(REG_MHL_ECBUS_2D, bEnableFlag? BIT(4): BIT(5), BMASK(5:4)); in _mhal_mhl_BISTECbusEnable()
2290 W2BYTEMSK(REG_COMBO_PHY1_P0_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2292 W2BYTEMSK(REG_COMBO_PHY0_P0_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2294 W2BYTEMSK(REG_COMBO_PHY1_P0_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2295 W2BYTEMSK(REG_COMBO_PHY1_P0_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2296 W2BYTEMSK(REG_COMBO_PHY1_P0_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2297 W2BYTEMSK(REG_COMBO_PHY1_P0_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2298 W2BYTEMSK(REG_COMBO_PHY0_P0_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2305 W2BYTEMSK(REG_COMBO_PHY1_P1_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2307 W2BYTEMSK(REG_COMBO_PHY0_P1_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2309 W2BYTEMSK(REG_COMBO_PHY1_P1_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2310 W2BYTEMSK(REG_COMBO_PHY1_P1_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2311 W2BYTEMSK(REG_COMBO_PHY1_P1_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2312 W2BYTEMSK(REG_COMBO_PHY1_P1_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2313 W2BYTEMSK(REG_COMBO_PHY0_P1_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2320 W2BYTEMSK(REG_COMBO_PHY1_P2_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2322 W2BYTEMSK(REG_COMBO_PHY0_P2_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2324 W2BYTEMSK(REG_COMBO_PHY1_P2_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2325 W2BYTEMSK(REG_COMBO_PHY1_P2_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2326 W2BYTEMSK(REG_COMBO_PHY1_P2_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2327 W2BYTEMSK(REG_COMBO_PHY1_P2_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2328 W2BYTEMSK(REG_COMBO_PHY0_P2_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2335 W2BYTEMSK(REG_COMBO_PHY1_P3_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2337 W2BYTEMSK(REG_COMBO_PHY0_P3_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2339 W2BYTEMSK(REG_COMBO_PHY1_P3_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2340 W2BYTEMSK(REG_COMBO_PHY1_P3_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2341 W2BYTEMSK(REG_COMBO_PHY1_P3_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2342 W2BYTEMSK(REG_COMBO_PHY1_P3_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2343 W2BYTEMSK(REG_COMBO_PHY0_P3_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2438 W2BYTEMSK(REG_COMBO_PHY0_P0_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2450 W2BYTEMSK(REG_COMBO_PHY0_P1_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2462 W2BYTEMSK(REG_COMBO_PHY0_P2_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2474 W2BYTEMSK(REG_COMBO_PHY0_P3_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2512 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2520 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2521 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2536 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2544 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2545 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2560 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2568 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2569 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2593 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2690 return (R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0)); in mhal_mhl_GetInputPort()
2728 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0); in mhal_mhl_CheckPIPWindow()
2729 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0); in mhal_mhl_CheckPIPWindow()
2731 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4; in mhal_mhl_CheckPIPWindow()
2755 …W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en… in mhal_mhl_MHLSupportPath()
3350 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3354 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3358 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3368 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3372 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3376 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3386 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3390 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3394 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3404 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3408 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3412 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3506 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
3607 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
3754 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3758 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3781 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3785 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3808 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3812 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3835 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3839 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
4146 … MHAL_MHL_MSG_DEBUG(" MHL send MSG command = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0))); in mhal_mhl_CBusWrite()
4150 … MHAL_MHL_MSG_DEBUG(" MHL send MSG data = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0))); in mhal_mhl_CBusWrite()
4457 if((ustemp & BMASK(1:0)) == 0x03) in mhal_mhl_RtermControlHWMode()
4544 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4548 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4658 …W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4674 …W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4690 …W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4706 …W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4887 …W2BYTEMSK(REG_MHL_ECBUS_2B, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist send… in mhal_mhl_SetBISTParameterInfo()
4888 …W2BYTEMSK(REG_MHL_ECBUS_2F, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist rece… in mhal_mhl_SetBISTParameterInfo()
5017 usEMSCFreeBuffer = (R2BYTE(REG_MHL_ECBUS_24) &BMASK(9:0)); // REG_MHL_ECBUS_24[9:0] in mhal_mhl_GetEMSCReceiveData()
5041 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0)); in mhal_mhl_GetEMSCReceiveData()
5062 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count in mhal_mhl_InsertEMSCSendData()
5063 …W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte c… in mhal_mhl_InsertEMSCSendData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()