| /rk3399_rockchip-uboot/drivers/reset/ |
| H A D | sandbox-reset.c | 20 struct sandbox_reset_signal signals[SANDBOX_RESET_SIGNALS]; member
46 sbr->signals[reset_ctl->id].asserted = true; in sandbox_reset_assert()
57 sbr->signals[reset_ctl->id].asserted = false; in sandbox_reset_deassert()
107 return sbr->signals[id].asserted; in sandbox_reset_query()
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| H A D | Kconfig | 10 controller drivers allow control over these reset signals. In some
22 controller drivers allow control over these reset signals. In some
40 Say Y if you want to control reset signals provided by system config
47 Enable support for manipulating Tegra's on-SoC reset signals via
54 Enable support for manipulating Tegra's on-SoC reset signals via IPC
69 Say Y if you want to control reset signals provided by System Control
80 is that some reset signals, like I2C or MISC reset multiple devices.
88 is that some reset signals, like I2C or MISC reset multiple devices.
95 is that some reset signals, like I2C or MISC reset multiple devices.
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/reset/ |
| H A D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
24 may be reset. Instead, reset signals should be represented in the DT node
27 block node for dedicated reset signals. The intent of this binding is to give
28 appropriate software access to the reset signals in order to manage the HW,
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
54 Each GPIO controller in fact generates multiple interrupts signals for each set
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
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| /rk3399_rockchip-uboot/board/congatec/conga-qeval20-qa3-e3845/ |
| H A D | README | 22 this case. The signals need to get connected directly to the
23 RS232 level signals of the PC UART via some adapter cable.
|
| /rk3399_rockchip-uboot/board/freescale/ls1012ardb/ |
| H A D | README | 23 signals to
31 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
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| /rk3399_rockchip-uboot/drivers/video/bridge/ |
| H A D | Kconfig | 17 LVDS capability, or where LVDS requires too many signals to route
27 or where LVDS requires too many signals to route on the PCB.
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| /rk3399_rockchip-uboot/scripts/kconfig/ |
| H A D | qconf.h | 71 signals:
225 signals:
253 signals:
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| /rk3399_rockchip-uboot/board/freescale/mpc837xemds/ |
| H A D | README | 10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.N1213 | 14 interrupt controller with 6 hardware interrupt signals.
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| /rk3399_rockchip-uboot/board/freescale/mpc832xemds/ |
| H A D | README | 10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed
|
| /rk3399_rockchip-uboot/board/freescale/ls1012aqds/ |
| H A D | README | 24 signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
|
| /rk3399_rockchip-uboot/doc/device-tree-bindings/leds/ |
| H A D | leds-bcm6358.txt | 18 - brcm,clk-dat-low : Boolean, makes clock and data signals active low.
|
| /rk3399_rockchip-uboot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 49 IEEE Std. 1588 signals for test and measurement
54 - 6-layer routing (4-layer signals, 2-layer power and ground)
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| /rk3399_rockchip-uboot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 116 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 119 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.lsch3 | 341 the EVENTI(Sev) signals.
343 Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
|
| /rk3399_rockchip-uboot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| H A D | kwbimage-is2.cfg | 113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
| /rk3399_rockchip-uboot/doc/device-tree-bindings/pinctrl/ |
| H A D | rockchip,pinctrl.txt | 5 multiplexing the PAD input/output signals. For each PAD there are several
|