189c1e2daSStephen Warrenmenu "Reset Controller Support" 289c1e2daSStephen Warren 389c1e2daSStephen Warrenconfig DM_RESET 489c1e2daSStephen Warren bool "Enable reset controllers using Driver Model" 589c1e2daSStephen Warren depends on DM && OF_CONTROL 689c1e2daSStephen Warren help 789c1e2daSStephen Warren Enable support for the reset controller driver class. Many hardware 889c1e2daSStephen Warren modules are equipped with a reset signal, typically driven by some 989c1e2daSStephen Warren reset controller hardware module within the chip. In U-Boot, reset 1089c1e2daSStephen Warren controller drivers allow control over these reset signals. In some 1189c1e2daSStephen Warren cases this API is applicable to chips outside the CPU as well, 1289c1e2daSStephen Warren although driving such reset isgnals using GPIOs may be more 1389c1e2daSStephen Warren appropriate in this case. 1489c1e2daSStephen Warren 158fce363fSJoseph Chenconfig SPL_DM_RESET 168fce363fSJoseph Chen bool "Enable reset controllers using Driver Model in SPL" 178fce363fSJoseph Chen depends on SPL_DM && OF_CONTROL 188fce363fSJoseph Chen help 198fce363fSJoseph Chen Enable support for the reset controller driver class. Many hardware 208fce363fSJoseph Chen modules are equipped with a reset signal, typically driven by some 218fce363fSJoseph Chen reset controller hardware module within the chip. In U-Boot, reset 228fce363fSJoseph Chen controller drivers allow control over these reset signals. In some 238fce363fSJoseph Chen cases this API is applicable to chips outside the CPU as well, 248fce363fSJoseph Chen although driving such reset isgnals using GPIOs may be more 258fce363fSJoseph Chen appropriate in this case. 268fce363fSJoseph Chen 274581b717SStephen Warrenconfig SANDBOX_RESET 284581b717SStephen Warren bool "Enable the sandbox reset test driver" 294581b717SStephen Warren depends on DM_MAILBOX && SANDBOX 304581b717SStephen Warren help 314581b717SStephen Warren Enable support for a test reset controller implementation, which 324581b717SStephen Warren simply accepts requests to reset various HW modules without actually 334581b717SStephen Warren doing anything beyond a little error checking. 344581b717SStephen Warren 35584861ffSPatrice Chotardconfig STI_RESET 36584861ffSPatrice Chotard bool "Enable the STi reset" 37584861ffSPatrice Chotard depends on ARCH_STI 38584861ffSPatrice Chotard help 39584861ffSPatrice Chotard Support for reset controllers on STMicroelectronics STiH407 family SoCs. 40584861ffSPatrice Chotard Say Y if you want to control reset signals provided by system config 41584861ffSPatrice Chotard block. 42584861ffSPatrice Chotard 43fe60f06dSStephen Warrenconfig TEGRA_CAR_RESET 44fe60f06dSStephen Warren bool "Enable Tegra CAR-based reset driver" 45fe60f06dSStephen Warren depends on TEGRA_CAR 46fe60f06dSStephen Warren help 47fe60f06dSStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via 48fe60f06dSStephen Warren direct register access to the Tegra CAR (Clock And Reset controller). 49fe60f06dSStephen Warren 504dd99d14SStephen Warrenconfig TEGRA186_RESET 514dd99d14SStephen Warren bool "Enable Tegra186 BPMP-based reset driver" 524dd99d14SStephen Warren depends on TEGRA186_BPMP 534dd99d14SStephen Warren help 544dd99d14SStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via IPC 554dd99d14SStephen Warren requests to the BPMP (Boot and Power Management Processor). 564dd99d14SStephen Warren 5718393f70SÁlvaro Fernández Rojasconfig RESET_BCM6345 5818393f70SÁlvaro Fernández Rojas bool "Reset controller driver for BCM6345" 5918393f70SÁlvaro Fernández Rojas depends on DM_RESET && ARCH_BMIPS 6018393f70SÁlvaro Fernández Rojas help 6118393f70SÁlvaro Fernández Rojas Support reset controller on BCM6345. 6218393f70SÁlvaro Fernández Rojas 634fb96c48SMasahiro Yamadaconfig RESET_UNIPHIER 644fb96c48SMasahiro Yamada bool "Reset controller driver for UniPhier SoCs" 654fb96c48SMasahiro Yamada depends on ARCH_UNIPHIER 664fb96c48SMasahiro Yamada default y 674fb96c48SMasahiro Yamada help 684fb96c48SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 694fb96c48SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 704fb96c48SMasahiro Yamada block, Media I/O block, Peripheral Block. 714fb96c48SMasahiro Yamada 72858d4976Smaxims@google.comconfig AST2500_RESET 73858d4976Smaxims@google.com bool "Reset controller driver for AST2500 SoCs" 74858d4976Smaxims@google.com depends on DM_RESET && WDT_ASPEED 75858d4976Smaxims@google.com default y if ASPEED_AST2500 76858d4976Smaxims@google.com help 77858d4976Smaxims@google.com Support for reset controller on AST2500 SoC. This controller uses 78858d4976Smaxims@google.com watchdog to reset different peripherals and thus only supports 79858d4976Smaxims@google.com resets that are supported by watchdog. The main limitation though 80858d4976Smaxims@google.com is that some reset signals, like I2C or MISC reset multiple devices. 81858d4976Smaxims@google.com 825754b8c9SElaine Zhangconfig RESET_ROCKCHIP 835754b8c9SElaine Zhang bool "Reset controller driver for Rockchip SoCs" 845754b8c9SElaine Zhang depends on DM_RESET && CLK 855754b8c9SElaine Zhang default y 865754b8c9SElaine Zhang help 875754b8c9SElaine Zhang Support for reset controller on rockchip SoC. The main limitation though 885754b8c9SElaine Zhang is that some reset signals, like I2C or MISC reset multiple devices. 895754b8c9SElaine Zhang 908fce363fSJoseph Chenconfig SPL_RESET_ROCKCHIP 918fce363fSJoseph Chen bool "Reset controller driver for Rockchip SoCs in SPL" 928fce363fSJoseph Chen depends on SPL_DM_RESET && SPL_CLK 938fce363fSJoseph Chen help 948fce363fSJoseph Chen Support for reset controller on rockchip SoC. The main limitation though 958fce363fSJoseph Chen is that some reset signals, like I2C or MISC reset multiple devices. 96*3cdb50e6SEtienne Carriere 97*3cdb50e6SEtienne Carriereconfig RESET_SCMI 98*3cdb50e6SEtienne Carriere bool "Enable SCMI reset domain driver" 99*3cdb50e6SEtienne Carriere select SCMI_FIRMWARE 100*3cdb50e6SEtienne Carriere help 101*3cdb50e6SEtienne Carriere Enable this option if you want to support reset controller 102*3cdb50e6SEtienne Carriere devices exposed by a SCMI agent based on SCMI reset domain 103*3cdb50e6SEtienne Carriere protocol communication with a SCMI server. 10489c1e2daSStephen Warrenendmenu 105