| /rk3399_rockchip-uboot/lib/optee_clientApi/ |
| H A D | OpteeClientSMC.c | 18 static void SetTeeSmc32Params(TEEC_Operation *operation,
21 TEEC_Operation *operation);
47 TEEC_Operation *operation, in TEEC_SMC_OpenSession() argument
116 SetTeeSmc32Params(operation, TeeSmc32Param + MetaNum); in TEEC_SMC_OpenSession()
128 GetTeeSmc32Params(TeeSmc32Param + MetaNum, operation); in TEEC_SMC_OpenSession()
195 TEEC_Operation *operation, in TEEC_SMC_InvokeCommand() argument
225 SetTeeSmc32Params(operation, TeeSmc32Param); in TEEC_SMC_InvokeCommand()
236 GetTeeSmc32Params(TeeSmc32Param, operation); in TEEC_SMC_InvokeCommand()
253 TEEC_Result TEEC_SMC_RequestCancellation(TEEC_Operation *operation, in TEEC_SMC_RequestCancellation() argument
268 void SetTeeSmc32Params(TEEC_Operation *operation, in SetTeeSmc32Params() argument
[all …]
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| H A D | OpteeClientApiLib.c | 329 TEEC_Operation *operation, in TEEC_OpenSession() argument
350 if (operation == NULL) { in TEEC_OpenSession()
354 TeecOperation = operation; in TEEC_OpenSession()
396 TEEC_Operation *operation, in TEEC_InvokeCommand() argument
413 if (operation == NULL) in TEEC_InvokeCommand()
416 TeecOperation = operation; in TEEC_InvokeCommand()
434 void TEEC_RequestCancellation(TEEC_Operation *operation) in TEEC_RequestCancellation() argument
439 if (operation == NULL) in TEEC_RequestCancellation()
442 TeecResult = TEEC_SMC_RequestCancellation(operation, &TeecErrorOrigin); in TEEC_RequestCancellation()
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| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/ |
| H A D | cache-uniphier.c | 96 u32 operation) in uniphier_cache_maint_common() argument
103 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM); in uniphier_cache_maint_common()
106 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) { in uniphier_cache_maint_common()
112 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) in uniphier_cache_maint_common()
122 static void uniphier_cache_maint_all(u32 operation) in uniphier_cache_maint_all() argument
124 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); in uniphier_cache_maint_all()
130 u32 operation) in uniphier_cache_maint_range() argument
144 uniphier_cache_maint_all(operation); in uniphier_cache_maint_range()
158 UNIPHIER_SSCOQM_S_RANGE | operation); in uniphier_cache_maint_range()
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| /rk3399_rockchip-uboot/include/optee_include/ |
| H A D | OpteeClientSMC.h | 16 TEEC_Operation * operation,
24 TEEC_Operation *operation,
27 TEEC_Result TEEC_SMC_RequestCancellation(TEEC_Operation *operation,
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| H A D | tee_client_api.h | 433 TEEC_Operation *operation,
463 TEEC_Operation *operation,
509 void TEEC_RequestCancellation(TEEC_Operation *operation);
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/misc/ |
| H A D | cros-ec.txt | 4 The device tree node which describes the operation of the CROS_EC interface
12 operation
14 operation
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| H A D | intel-lpc.txt | 4 The device tree node which describes the operation of the Intel Low Pin
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.fuse | 7 (i.e. blown, set to 1) only once. The programming operation is irreversible. A
34 fuse words. This operation does not update the shadow cache.
41 Program fuse words. This operation directly affects the fusebox and is
49 hardware programming operation on these fuse bits).
55 The fusebox is unaffected, so following this operation, the shadow cache
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| H A D | README.fsl_iim | 37 this operation, the shadow registers are reloaded by the hardware (not
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| H A D | README.mxc_ocotp | 41 Following this operation, the shadow registers are not reloaded by the
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| /rk3399_rockchip-uboot/drivers/mtd/nand/raw/ |
| H A D | mxc_nand_spl.c | 123 writenfc(NFC_CMD, &nfc->operation); in nfc_nand_command()
130 writenfc(NFC_ADDR, &nfc->operation); in nfc_nand_address()
171 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
180 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
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| H A D | mxc_nand.h | 200 #define operation config2 macro
204 #define operation launch macro
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| H A D | mxc_nand.c | 149 writenfc(NFC_CMD, &host->regs->operation);
165 writenfc(NFC_ADDR, &host->regs->operation);
216 writenfc(NFC_INPUT, &host->regs->operation);
250 writenfc(NFC_OUTPUT, &host->regs->operation);
291 writenfc(NFC_ID, &host->regs->operation);
322 writenfc(NFC_STATUS, &host->regs->operation);
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| /rk3399_rockchip-uboot/lib/efi_loader/ |
| H A D | efi_gop.c | 60 unsigned long operation, unsigned long sx, in gop_blt() argument
70 buffer, operation, sx, sy, dx, dy, width, height, delta); in gop_blt()
72 if (operation != EFI_BLT_BUFFER_TO_VIDEO) in gop_blt()
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| /rk3399_rockchip-uboot/drivers/usb/dwc3/ |
| H A D | Kconfig | 45 This wrapper supports Host and Peripheral operation modes.
53 This wrapper supports Host and Peripheral operation modes.
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/ |
| H A D | tegra20-i2c.txt | 9 - the pll_p_out3 clock, which can be used for fast operation. This
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| H A D | i2c-stm32.txt | 9 operation for I2C transfer
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 36 - Three PCIe 2.0 controllers, one supporting x4 operation
103 16-/8-bit operation (no ECC support)
110 Support for up to 6 GBaud operation
112 - One PCI Express Gen2 controller, supporting x1 operation
155 - Support for 10G operation
163 - Three PCIe 3.0 controllers, one supporting x4 operation
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/ata/ |
| H A D | intel-sata.txt | 4 The device tree node which describes the operation of the Intel Pantherpoint
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| /rk3399_rockchip-uboot/arch/mips/cpu/ |
| H A D | start.S | 50 li t9, 15 # UHI exception operation
52 sdbbp 1 # Invoke UHI operation
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| /rk3399_rockchip-uboot/board/ti/omap5_uevm/ |
| H A D | README | 12 Alternative Boot operation mode or Boot Sequence Option 1/2. In this
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| /rk3399_rockchip-uboot/board/ti/dra7xx/ |
| H A D | README | 12 Alternative Boot operation mode or Boot Sequence Option 1/2. In this
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_ip_engine.h | 50 enum hws_training_load_op operation,
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3368-dmc.txt | 7 (a) a target-frequency (i.e. operating point) for the memory operation
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/net/ |
| H A D | ethernet.txt | 12 - phy-mode: string, operation mode of the PHY interface; supported values are
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