Searched refs:GPIO1_IOC_BASE (Results 1 – 5 of 5) sorted by relevance
32 #define GPIO1_IOC_BASE 0x20170000 macro83 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0); in board_set_iomux()84 writel(0x00ff0011, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0); in board_set_iomux()88 writel(0xf0000000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1); in board_set_iomux()89 writel(0xffff0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0); in board_set_iomux()90 writel(0x000f0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1); in board_set_iomux()91 writel(0xc0008000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1); in board_set_iomux()92 writel(0x03ff02AA, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL); in board_set_iomux()101 writel(0xff001100, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1); in board_set_iomux()102 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0); in board_set_iomux()[all …]
77 #define GPIO1_IOC_BASE 0xFF560000 macro82 #define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)83 #define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)84 #define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)85 #define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)86 #define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)87 #define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)112 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)116 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)140 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)[all …]
136 #define GPIO1_IOC_BASE 0xFF060000 macro165 #define UART0_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)169 #define UART0_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)175 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x18)179 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x18)241 #define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)245 #define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)251 #define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0xC)255 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x10)298 #define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)[all …]
122 #define GPIO1_IOC_BASE 0xFF538000 macro151 #define UART0_RX_M0_ADDR (GPIO1_IOC_BASE)155 #define UART0_TX_M0_ADDR (GPIO1_IOC_BASE)179 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x4)183 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE)216 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x8)220 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x8)226 #define UART3_RX_M0_ADDR (GPIO1_IOC_BASE)230 #define UART3_TX_M0_ADDR (GPIO1_IOC_BASE)235 #define UART3_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)[all …]
37 #define GPIO1_IOC_BASE 0xff660000 macro