1 /*
2 * Copyright (c) 2024 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <spl.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/grf_rv1103b.h>
13 #include <asm/arch/ioc_rv1103b.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #define PERI_CRU_BASE 0x20000000
18 #define PERICRU_PERISOFTRST_CON10 0x0a28
19
20 #define PMU0_CRU_BASE 0x20070000
21 #define PMUCRU_PMUSOFTRST_CON02 0x0a08
22
23 #define GRF_SYS_BASE 0x20150000
24 #define GRF_SYS_HPMCU_CACHE_MISC 0x0214
25
26 #define GPIO0_IOC_BASE 0x201B0000
27 #define GPIO0A_IOMUX_SEL_H 0x04
28 #define GPIO0_BASE 0x20520000
29 #define GPIO_SWPORT_DR_L 0x00
30 #define GPIO_SWPORT_DDR_L 0x08
31
32 #define GPIO1_IOC_BASE 0x20170000
33 #define GPIO1A_IOMUX_SEL_0 0x20
34 #define GPIO1A_IOMUX_SEL_1_0 0x24
35 #define GPIO1A_IOMUX_SEL_1_1 0x10024
36 #define GPIO1B_IOMUX_SEL_0 0x10028
37 #define GPIO1B_IOMUX_SEL_1 0x1002c
38 #define GPIO1_IOC_GPIO1A_PULL_0 0x210
39 #define GPIO1_IOC_GPIO1A_PULL_1 0x10210
40 #define GPIO1_IOC_GPIO1B_PULL 0x10214
41 #define GPIO1_IOC_JTAG_M2_CON 0x10810
42
43 #define GPIO2_IOC_BASE 0x20840000
44 #define GPIO2A_IOMUX_SEL_1_1 0x44
45
46 #define SGRF_SYS_BASE 0x20250000
47 #define SGRF_SYS_SOC_CON2 0x0008
48 #define SGRF_SYS_SOC_CON3 0x000c
49 #define SGRF_SYS_OTP_CON 0x0018
50 #define FIREWALL_CON0 0x0020
51 #define FIREWALL_CON1 0x0024
52 #define FIREWALL_CON2 0x0028
53 #define FIREWALL_CON3 0x002c
54 #define FIREWALL_CON4 0x0030
55 #define FIREWALL_CON5 0x0034
56 #define FIREWALL_CON7 0x003c
57 #define SGRF_SYS_HPMCU_BOOT_DDR 0x0080
58
59 #define SGRF_PMU_BASE 0x20260000
60 #define SGRF_PMU_SOC_CON0 0x0000
61 #define SGRF_PMU_PMUMCU_BOOT_ADDR 0x0020
62
63 #define SYS_GRF_BASE 0x20150000
64 #define GRF_SYS_PERI_CON2 0x08
65 #define GRF_SYS_USBPHY_CON0 0x50
66
67 #define TOP_CRU_BASE 0x20060000
68 #define TOPCRU_CRU_GLB_RST_CON 0xc10
69
70 #define USBPHY_APB_BASE 0x20e10000
71 #define USBPHY_FSLS_DIFF_RECEIVER 0x0100
72
board_debug_uart_init(void)73 void board_debug_uart_init(void)
74 {
75 /* No need to change uart */
76 }
77
board_set_iomux(enum if_type if_type,int devnum,int routing)78 void board_set_iomux(enum if_type if_type, int devnum, int routing)
79 {
80 switch (if_type) {
81 case IF_TYPE_MMC:
82 if (devnum == 0) {
83 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0);
84 writel(0x00ff0011, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
85 } else if (devnum == 1) {
86 #if CONFIG_SPL_BUILD
87 /* set SDMMC D0-3/CMD/CLK to gpio and pull down */
88 writel(0xf0000000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1);
89 writel(0xffff0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0);
90 writel(0x000f0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1);
91 writel(0xc0008000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1);
92 writel(0x03ff02AA, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL);
93
94 /* SDMMC PWREN GPIO0A4 power down and power up */
95 writel(0x00100010, GPIO0_BASE + GPIO_SWPORT_DR_L);
96 writel(0x00100010, GPIO0_BASE + GPIO_SWPORT_DDR_L);
97 mdelay(50);
98 writel(0x00100000, GPIO0_BASE + GPIO_SWPORT_DR_L);
99 #endif
100 /* set SDMMC D0-3/CMD/CLK and pull up */
101 writel(0xff001100, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1);
102 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0);
103 writel(0x000f0001, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1);
104 writel(0xc0004000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1);
105 writel(0x03ff0155, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL);
106 }
107 break;
108 case IF_TYPE_MTD:
109 if (routing == 0) {
110 /* FSPI0 M0 */
111 writel(0xffff2222, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0);
112 writel(0x00ff0022, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
113 }
114 break;
115 default:
116 printf("Bootdev 0x%x is not support\n", if_type);
117 }
118 }
119
120 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)121 void rockchip_stimer_init(void)
122 {
123 /* If Timer already enabled, don't re-init it */
124 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
125 if (reg & 0x1)
126 return;
127 writel(0x00010000, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
128
129 asm volatile("mcr p15, 0, %0, c14, c0, 0"
130 : : "r"(COUNTER_FREQUENCY));
131 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
132 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
133 writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
134 }
135
spl_fit_standalone_release(char * id,uintptr_t entry_point)136 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
137 {
138 if (!strcmp(id, "mcu0")) {
139 /* set the hpmcu boot address */
140 writel(entry_point, SGRF_SYS_BASE + SGRF_SYS_HPMCU_BOOT_DDR);
141 } else if (!strcmp(id, "mcu1")) {
142 /* reset lpmcu */
143 writel(0x000f000f, PMU0_CRU_BASE + PMUCRU_PMUSOFTRST_CON02);
144 /* set the lpmcu boot address */
145 writel(entry_point, SGRF_PMU_BASE + SGRF_PMU_PMUMCU_BOOT_ADDR);
146 writel(0x00800000, SGRF_PMU_BASE + SGRF_PMU_SOC_CON0);
147 /* release lpmcu */
148 writel(0x000f0000, PMU0_CRU_BASE + PMUCRU_PMUSOFTRST_CON02);
149 }
150
151 return 0;
152 }
153
rk_meta_process(void)154 void rk_meta_process(void)
155 {
156 /* trigger software irq to hpmcu that means meta was ready */
157 writel(0x00080008, GRF_SYS_BASE + GRF_SYS_HPMCU_CACHE_MISC);
158 }
159 #endif
160
161 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)162 int arch_cpu_init(void)
163 {
164 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
165 /* Set all devices to Non-secure */
166 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON0);
167 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON1);
168 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON2);
169 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON3);
170 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON4);
171 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON5);
172 writel(0x01f00000, SGRF_SYS_BASE + FIREWALL_CON7);
173 /* Set OTP to none secure mode */
174 writel(0x00020000, SGRF_SYS_BASE + SGRF_SYS_OTP_CON);
175
176 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
177 /* Set the emmc iomux */
178 board_set_iomux(IF_TYPE_MMC, 0, 0);
179 #elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
180 /* Set the fspi iomux */
181 board_set_iomux(IF_TYPE_MTD, 0, 0);
182 #endif
183
184 #if defined(CONFIG_MMC_DW_ROCKCHIP)
185 /* Set the sdmmc iomux and power cycle */
186 board_set_iomux(IF_TYPE_MMC, 1, 0);
187 /* Enable force_jtag */
188 writel(0x00010001, GPIO1_IOC_BASE + GPIO1_IOC_JTAG_M2_CON);
189 #endif
190
191 /* no-secure WDT reset output will reset SoC system. */
192 writel(0x00010001, SYS_GRF_BASE + GRF_SYS_PERI_CON2);
193 /* secure WDT reset output will reset SoC system. */
194 writel(0x00010001, SGRF_SYS_BASE + SGRF_SYS_SOC_CON2);
195 /*
196 * enable tsadc trigger global reset and select first reset.
197 * enable global reset and wdt trigger pmu reset.
198 * select first reset trigger pmu reset.
199 */
200 writel(0x0000ffdf, TOP_CRU_BASE + TOPCRU_CRU_GLB_RST_CON);
201
202 /*
203 * Set the USB2 PHY in suspend mode and turn off the
204 * USB2 PHY FS/LS differential receiver to save power:
205 * VCC1V8_USB : reduce 3.8 mA
206 * VDD_0V9 : reduce 4.4 mA
207 */
208 writel(0x01ff01d1, SYS_GRF_BASE + GRF_SYS_USBPHY_CON0);
209 writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);
210
211 #ifdef CONFIG_SPI_FLASH_AUTO_MERGE
212 /* gpio1a5/gpio2a6 cs-gpio */
213 writel(0x00F00000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
214 writel(0x0F000000, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_1_1);
215 #endif
216 #endif
217
218 return 0;
219 }
220 #endif
221
222 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
rk_board_scan_bootdev(void)223 int rk_board_scan_bootdev(void)
224 {
225 char *devtype, *devnum;
226
227 if (!run_command("blk dev mmc 1", 0) &&
228 !run_command("rkimgtest mmc 1", 0)) {
229 devtype = "mmc";
230 devnum = "1";
231 } else {
232 run_command("blk dev mtd 2", 0);
233 devtype = "mtd";
234 devnum = "2";
235 }
236 env_set("devtype", devtype);
237 env_set("devnum", devnum);
238
239 return 0;
240 }
241 #endif
242
243 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) && defined(CONFIG_ROCKCHIP_SFC_IOMUX)
244 #error FSPI and eMMC iomux is incompatible for rv1103b Soc. You should close one of them.
245 #endif
246