Lines Matching refs:GPIO1_IOC_BASE
122 #define GPIO1_IOC_BASE 0xFF538000 macro
151 #define UART0_RX_M0_ADDR (GPIO1_IOC_BASE)
155 #define UART0_TX_M0_ADDR (GPIO1_IOC_BASE)
179 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x4)
183 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE)
216 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
220 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
226 #define UART3_RX_M0_ADDR (GPIO1_IOC_BASE)
230 #define UART3_TX_M0_ADDR (GPIO1_IOC_BASE)
235 #define UART3_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
245 #define UART4_RX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
249 #define UART4_TX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
254 #define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
258 #define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
268 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x44)
273 #define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
277 #define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x18)