Lines Matching refs:GPIO1_IOC_BASE
32 #define GPIO1_IOC_BASE 0x20170000 macro
83 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0); in board_set_iomux()
84 writel(0x00ff0011, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0); in board_set_iomux()
88 writel(0xf0000000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1); in board_set_iomux()
89 writel(0xffff0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0); in board_set_iomux()
90 writel(0x000f0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1); in board_set_iomux()
91 writel(0xc0008000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1); in board_set_iomux()
92 writel(0x03ff02AA, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL); in board_set_iomux()
101 writel(0xff001100, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1); in board_set_iomux()
102 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0); in board_set_iomux()
103 writel(0x000f0001, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1); in board_set_iomux()
104 writel(0xc0004000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1); in board_set_iomux()
105 writel(0x03ff0155, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL); in board_set_iomux()
111 writel(0xffff2222, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0); in board_set_iomux()
112 writel(0x00ff0022, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0); in board_set_iomux()
188 writel(0x00010001, GPIO1_IOC_BASE + GPIO1_IOC_JTAG_M2_CON); in arch_cpu_init()
213 writel(0x00F00000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0); in arch_cpu_init()