Searched refs:read_midr (Results 1 – 17 of 17) sorted by relevance
34 unsigned int midr = (unsigned int)read_midr(); in check_cpupwrctrl_el1_is_available()
61 switch (EXTRACT_PARTNUM(read_midr())) { in check_if_trbe_disable_affected_core()93 switch (EXTRACT_PARTNUM(read_midr())) { in errata_ich_vmcr_el2_applies()
24 midr = (unsigned int)read_midr(); in midr_match()
259 write_vpidr(read_midr()); in cm_prepare_el3_exit()
118 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in mce_get_curr_cpu_ari_base()138 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & in mce_get_curr_cpu_ops()
207 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in nvg_online_core()
330 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in ari_online_core()
378 impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_on_finish()448 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
204 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in plat_early_platform_setup()
137 uint32_t midr_val = read_midr(); in non_arm_interconnect_errata()
189 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) in bl31_early_platform_setup2()
227 midr = read_midr(); in hikey_boardid_init()
166 read_midr() == CORTEX_A53_MIDR); in tegra_fc_cluster_powerdn()
478 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
710 reg = read_midr(); in bl2_el3_early_platform_setup()
951 #define read_midr() read_midr_el1() macro
1079 reg = read_midr(); in bl2_el3_early_platform_setup()