Merge changes from topic "ar/cve_wa_refactor" into integration

* changes:
refactor(cpus): optimize CVE checking
refactor(cpus): move errata check to common code
refactor(cpus): drop unused arg

Merge changes from topic "ar/cve_wa_refactor" into integration

* changes:
refactor(cpus): optimize CVE checking
refactor(cpus): move errata check to common code
refactor(cpus): drop unused argument forward_flag

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refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is

refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is mostly generic.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2c6d4468f7125d4d99ccdebc5ea8f9e4390360cc

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refactor(cpus): drop unused argument forward_flag

This patch removes the unused argument forward_flag
from verify_errata_implemented function.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@a

refactor(cpus): drop unused argument forward_flag

This patch removes the unused argument forward_flag
from verify_errata_implemented function.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ib1fcbe081e94657e21d983e0db59ceec9993b696

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Merge "fix(errata-abi): add support for handling split workarounds" into integration

fix(errata-abi): add support for handling split workarounds

Certain erratum workarounds like Neoverse N1 1542419, need a part
of their mitigation done in EL3 and the rest in lower EL. But currently

fix(errata-abi): add support for handling split workarounds

Certain erratum workarounds like Neoverse N1 1542419, need a part
of their mitigation done in EL3 and the rest in lower EL. But currently
such workarounds return HIGHER_EL_MITIGATION which indicates that the
erratum has already been mitigated by a higher EL(EL3 in this case)
which causes the lower EL to not apply it's part of the mitigation.

This patch fixes this issue by adding support for split workarounds
so that on certain errata we return AFFECTED even though EL3 has
applied it's workaround. This is done by reusing the chosen field of
erratum_entry structure into a bitfield that has two bitfields -
Bit 0 indicates that the erratum has been enabled in build,
Bit 1 indicates that the erratum is a split workaround and should
return AFFECTED instead of HIGHER_EL_MITIGATION.

SDEN documentation:
https://developer.arm.com/documentation/SDEN885747/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iec94d665b5f55609507a219a7d1771eb75e7f4a7

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Merge "chore(errata-abi): minor variable rename" into integration

chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr v

chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.

So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.

Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(cpus): workaround for Cortex-X4 erratum 2701112" into integration

fix(cpus): workaround for Cortex-X4 erratum 2701112

Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do

fix(cpus): workaround for Cortex-X4 erratum 2701112

Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do not use an Arm interconnect IP.

The workaround for this erratum is not implemented in EL3.
The erratum can be enabled/disabled on a platform level.
The flag is used when the errata ABI feature is enabled and can
assist the Kernel in the process of mitigation of the erratum.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi)

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi): workaround platforms non-arm interconnect
refactor(errata-abi): optimize errata ABI using errata framework

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fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Corte

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level

refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structur

refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.

Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2429384" into integration

fix(cpus): workaround for Cortex-A715 erratum 2429384

Cortex-A715 erratum 2429384 is a cat B erratum that applies to
revision r1p0 and is fixed in r1p1. The workaround is to set
bit[27] of CPUACTLR2

fix(cpus): workaround for Cortex-A715 erratum 2429384

Cortex-A715 erratum 2429384 is a cat B erratum that applies to
revision r1p0 and is fixed in r1p1. The workaround is to set
bit[27] of CPUACTLR2_EL1. There is no workaround for revision
r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I3cdb1b71567542174759f6946e9c81f77d0d993d
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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Merge "fix(cpus): workaround for Cortex-X3 erratum 2372204" into integration

fix(cpus): workaround for Cortex-X3 erratum 2372204

Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions
r0p0 and r1p0. It is fixed in r1p1.

The workaround is to set bit[40] of CP

fix(cpus): workaround for Cortex-X3 erratum 2372204

Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions
r0p0 and r1p0. It is fixed in r1p1.

The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Change-Id: Iad28f8625c84186fbd8049406d139d4f15c6e069
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2561034" into integration

fix(cpus): workaround for Cortex-A715 erratum 2561034

Cortex-A715 erratum 2561034 is a Cat B erratum that applies to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit[26] in CPUACTLR

fix(cpus): workaround for Cortex-A715 erratum 2561034

Cortex-A715 erratum 2561034 is a Cat B erratum that applies to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this
bit is not expected to have a significant performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(cpus): workaround for Cortex X3 erratum 2641945" into integration

fix(cpus): workaround for Cortex X3 erratum 2641945

Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.

The workaround is to disable the affecte

fix(cpus): workaround for Cortex X3 erratum 2641945

Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.

The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2683027
fix(cpus): workaround for Cortex-X3 erratum 2266875
fix(cpus): workaround fo

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2683027
fix(cpus): workaround for Cortex-X3 erratum 2266875
fix(cpus): workaround for Cortex-X3 erratum 2302506

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fix(cpus): workaround for Cortex-A78C erratum 2683027

Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific

fix(cpus): workaround for Cortex-A78C erratum 2683027

Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific code sequence in EL3 during reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2266875

Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]

fix(cpus): workaround for Cortex-X3 erratum 2266875

Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to
invalidate all branch predictor resources regardless of context.

SDEN Documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR

fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.

There might be a small performance degradation to this workaround
for certain workloads that share data.

SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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