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/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_sip_calls.c44 uint64_t per[3] = {0ULL}; in plat_sip_handler() local
63 per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); in plat_sip_handler()
64 per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); in plat_sip_handler()
65 per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); in plat_sip_handler()
68 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); in plat_sip_handler()
69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
70 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); in plat_sip_handler()
/rk3399_ARM-atf/docs/components/
H A Dnuma-per-cpu.rst15 CPUs on remote nodes. In TF-A's current implementation, per-CPU data (for
22 node may be insufficient to hold per-CPU data for all CPUs. This constraint
25 .. figure:: ../resources/diagrams/per-cpu-numa-disabled.png
38 traversal. When per-CPU data is centralized on a single node, CPUs on remote
45 framework optimizes the allocation and access of per-CPU objects by letting
52 **allocating**, **defining**, and **accessing** per-CPU data in a NUMA-aware
60 to **allocate** per-CPU global variables and ensure that these objects reside in
61 the local memory of each NUMA node. The figure below illustrates how per-CPU
64 .. figure:: ../resources/diagrams/per-cpu-numa-enabled.png
71 \`.bss\` and \`xlat\` to represent per-CPU data allocation, while
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H A Dindex.rst32 numa-per-cpu
H A Dactivity-monitors.rst24 ``plat_amu_aux_enables`` platform hook. This is a per-core array indexed with
H A Dmpmm.rst11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware.
H A Dcontext-management-library.rst14 are not banked per world. When moving between the security states it is the
243 per-CPU and per-world to accurately represent asymmetric
246 The per-cpu cached ID registers are initialized in ``psci_arch_setup()``
283 CPUs maintain their context per world. The individual context memory allocation
284 for each CPU per world is allocated by the world-specific dispatcher components
318 per-CPU data structures, which means that each CPU will have an array of pointers
414 world-specific context setup handlers listed above will be invoked once per-CPU
528 During initialization, the per-world ID register cache is populated by
H A Dgranule-protection-tables-design.rst265 by the size of memory block per bit. The size of memory block
266 is ``RME_GPT_BITLOCK_BLOCK`` (number of 512MB blocks per bit) times
286 And solve to get 0x20000 bytes per L1 table.
/rk3399_ARM-atf/fdts/
H A Dfvp-base-gicv3-psci-1t.dts7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
H A Dfvp-base-gicv3-psci-dynamiq-2t.dts7 /* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
H A Dfvp-base-gicv23-interrupts.dtsi45 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
H A Dfvp-defs.dtsi319 /* Max 4 CPUs per cluster */
H A Dstm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi14 * density 8Gbits (per 16bit channel)
H A Dstm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi14 * density 16Gbits (per 16bit channel)
/rk3399_ARM-atf/plat/nvidia/tegra/scat/
H A Dbl31.scat193 /* padded memory section to store per cpu bakery locks */
225 /* padded memory section to store per cpu timestamps */
/rk3399_ARM-atf/docs/plat/
H A Damd-versal2.rst49 The custom package can define the desired stack size as per the requirement in
105 | 0xC2000000-0xC200FFFF | Fast SMC64 SiP Service Calls as per SMCCC Section 6.1 |
H A Dxilinx-versal.rst66 The custom package can define the desired stack size as per the requirement in
130 | 0xC2000000-0xC200FFFF | Fast SMC64 SiP Service Calls as per SMCCC Section 6.1 |
H A Dxilinx-versal-net.rst71 | 0xC2000000-0xC200FFFF | Fast SMC64 SiP Service Calls as per SMCCC Section 6.1 |
H A Dxilinx-zynqmp.rst96 The custom package can define the desired stack size as per the requirement in
179 | 0xC2000000-0xC200FFFF | Fast SMC64 SiP Service Calls as per SMCCC Section 6.1 |
H A Dpoplar.rst12 video at 60 frames per second.
/rk3399_ARM-atf/
H A D.editorconfig66 # "Use 4 spaces per indentation level."
/rk3399_ARM-atf/docs/process/
H A Dmaintenance.rst34 - Having appropriate bandwidth (minimum 2 hours per week) to deal with the workload.
/rk3399_ARM-atf/docs/components/fconf/
H A Dtb_fw_bindings.rst142 images, and non-volatile counters defined as per the specifications therein.
/rk3399_ARM-atf/docs/design/
H A Dfirmware-design.rst499 BL31 initializes the per-CPU data framework, which provides a cache of
500 frequently accessed per-CPU data optimised for fast, concurrent manipulation
501 on different CPUs. This buffer includes pointers to per-CPU contexts, crash
928 uses per-CPU data this must either be initialized for all CPUs during this call,
955 Function ID is passed in W0 from the lower exception level (as per the
973 and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets
1239 A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1240 the per-CPU pointer cache. The implementation attempts to minimise the memory
1504 entry is stored in per-CPU data by ``cpu_data_init_cpu_ops()`` so that it can be quickly
1512 retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
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H A Dinterrupt-framework-design.rst328 interrupt was generated and routed as per the routing model specified
510 will be routed to EL3 (as per the routing model where **CSS=1 and
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
635 upon exception entry. The registers are saved in the per-cpu ``cpu_context``
639 per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
642 from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
675 The handler function returns a reference to the per-cpu ``cpu_context_t``
728 per the synchronous interrupt handling model it implements. A Secure-EL1
735 #. Setting the return value of the handler to the per-cpu ``cpu_context`` if
787 #. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-8.rst31 As per the `SMC Calling Convention`_, up to 4 values may be returned to the

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