168120783SChris KayMaximum Power Mitigation Mechanism (MPMM) 268120783SChris Kay^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 368120783SChris Kay 468120783SChris Kay|MPMM| is an optional microarchitectural power management mechanism supported by 568120783SChris Kaysome Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and 668120783SChris KayCortex-A510 cores. This mechanism detects and limits high-activity events to 768120783SChris Kayassist in |SoC| processor power domain dynamic power budgeting and limit the 868120783SChris Kaytriggering of whole-rail (i.e. clock chopping) responses to overcurrent 968120783SChris Kayconditions. 1068120783SChris Kay 11*2590e819SBoyan Karatotev|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. 1268120783SChris Kay 1368120783SChris Kay.. warning:: 1468120783SChris Kay 1568120783SChris Kay |MPMM| exposes gear metrics through the auxiliary |AMU| counters. An 1668120783SChris Kay external power controller can use these metrics to budget SoC power by 1768120783SChris Kay limiting the number of cores that can execute higher-activity workloads or 1868120783SChris Kay switching to a different DVFS operating point. When this is the case, the 1968120783SChris Kay |AMU| counters that make up the |MPMM| gears must be enabled by the EL3 2068120783SChris Kay runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for 2168120783SChris Kay documentation on enabling auxiliary |AMU| counters. 22