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Searched refs:gicr_base (Results 1 – 25 of 37) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/gic600/
H A Dmt_gic_v3.c41 .gicr_base = MT_GIC_RDIST_BASE,
92 uintptr_t gicr_base; in mt_gic_rdistif_init() local
95 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
98 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
99 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
103 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
110 uintptr_t gicr_base; in mt_gic_rdistif_save() local
113 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
119 gicr_wait_for_pending_write(gicr_base); in mt_gic_rdistif_save()
121 gic_data.saved_ctlr = mmio_read_32(gicr_base + GICR_CTLR); in mt_gic_rdistif_save()
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/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Darm_gicv3_common.c30 uintptr_t gicr_base = 0; in arm_gicv3_distif_pre_save() local
44 gicr_base = gicv3_driver_data->rdistif_base_addrs[i]; in arm_gicv3_distif_pre_save()
45 assert(gicr_base != 0U); in arm_gicv3_distif_pre_save()
46 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); in arm_gicv3_distif_pre_save()
47 assert((gicr_read_waker(gicr_base) & WAKER_PS_BIT) != 0U); in arm_gicv3_distif_pre_save()
50 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_pre_save()
64 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT); in arm_gicv3_distif_pre_save()
71 while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT)) { in arm_gicv3_distif_pre_save()
83 uintptr_t gicr_base; in arm_gicv3_distif_post_restore() local
93 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_post_restore()
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H A Dgic-x00.c110 uintptr_t gicr_base; in get_gicr_base() local
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in get_gicr_base()
117 assert(gicr_base != 0UL); in get_gicr_base()
119 return gicr_base; in get_gicr_base()
122 static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base) in gicv3_redists_need_power_mgmt() argument
124 uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); in gicv3_redists_need_power_mgmt()
154 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_off() local
157 if (gicv3_redists_need_power_mgmt(gicr_base)) { in gicv3_rdistif_off()
158 gic600_pwr_off(gicr_base); in gicv3_rdistif_off()
169 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_on() local
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H A Dgicv3_helpers.c36 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) in gicv3_rdistif_mark_core_awake() argument
38 uint32_t waker = gicr_read_waker(gicr_base); in gicv3_rdistif_mark_core_awake()
51 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { in gicv3_rdistif_mark_core_awake()
56 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); in gicv3_rdistif_mark_core_awake()
59 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { in gicv3_rdistif_mark_core_awake()
67 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) in gicv3_rdistif_mark_core_asleep() argument
70 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); in gicv3_rdistif_mark_core_asleep()
73 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { in gicv3_rdistif_mark_core_asleep()
84 uintptr_t gicr_base, in gicv3_rdistif_base_addrs_probe() argument
90 uintptr_t rdistif_base = gicr_base; in gicv3_rdistif_base_addrs_probe()
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H A Dgicv3_main.c140 if (plat_driver_data->gicr_base != 0U) { in gicv3_driver_init()
149 plat_driver_data->gicr_base, in gicv3_driver_init()
229 uintptr_t gicr_base; in gicv3_rdistif_init() local
246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_rdistif_init()
247 assert(gicr_base != 0U); in gicv3_rdistif_init()
250 gicv3_ppi_sgi_config_defaults(gicr_base); in gicv3_rdistif_init()
252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, in gicv3_rdistif_init()
279 uintptr_t gicr_base; in gicv3_cpuif_enable() local
289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_cpuif_enable()
290 gicv3_rdistif_mark_core_awake(gicr_base); in gicv3_cpuif_enable()
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H A Dgicv3_private.h241 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
242 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
250 uintptr_t gicr_base,
252 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
253 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
345 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) in gicr_wait_for_pending_write() argument
347 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { in gicr_wait_for_pending_write()
351 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) in gicr_wait_for_upstream_pending_write() argument
353 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { in gicr_wait_for_upstream_pending_write()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_mt_gic.c34 .gicr_base = MT_GIC_RDIST_BASE,
85 uintptr_t gicr_base; in mt_gic_rdistif_init() local
88 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
91 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
92 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
96 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
113 uintptr_t gicr_base; in mt_gic_rdistif_save() local
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
118 gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); in mt_gic_rdistif_save()
119 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
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/rk3399_ARM-atf/plat/arm/board/arm_fpga/
H A Dfpga_gicv3.c43 uintptr_t gicr_base = 0U; in plat_fpga_gic_init() local
71 gicr_base = fpga_gicv3_driver_data.gicd_base + (4U << 16); in plat_fpga_gic_init()
77 frame_id = gicv3_get_component_partnum(gicr_base); in plat_fpga_gic_init()
81 nr_itses, (unsigned long long)gicr_base); in plat_fpga_gic_init()
88 gicr_base = 0U; in plat_fpga_gic_init()
97 its_typer = mmio_read_64(gicr_base + GITS_TYPER); in plat_fpga_gic_init()
99 gicr_base += 4U << 16; in plat_fpga_gic_init()
101 gicr_base += 2U << 16; in plat_fpga_gic_init()
111 if (gicr_base == 0U) { in plat_fpga_gic_init()
113 &fpga_gicv3_driver_data.gicr_base, in plat_fpga_gic_init()
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/rk3399_ARM-atf/plat/qemu/qemu_sbsa/
H A Dsbsa_gic.c25 .gicr_base = GICR_BASE,
33 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base) in sbsa_set_gic_bases() argument
36 sbsa_gic_driver_data.gicr_base = gicr_base; in sbsa_set_gic_bases()
46 return sbsa_gic_driver_data.gicr_base; in sbsa_get_gicr()
H A Dsbsa_platform.c23 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
214 uintptr_t gicr_base; in read_platform_config_from_dt() local
244 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL); in read_platform_config_from_dt()
249 INFO("GICR base = 0x%lx\n", gicr_base); in read_platform_config_from_dt()
251 sbsa_set_gic_bases(gicd_base, gicr_base); in read_platform_config_from_dt()
/rk3399_ARM-atf/plat/ti/common/
H A Dk3_gicv3.c48 uintptr_t gicr_base = 0; in k3_gic_driver_init() local
55 gicr_base = gicr_check; in k3_gic_driver_init()
60 assert(gicr_base != 0); in k3_gic_driver_init()
69 k3_gic_data.gicr_base = gicr_base; in k3_gic_driver_init()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_bl31_setup.c110 uintptr_t gicr_base; in bl31_platform_setup() local
119 gic_data.gicr_base = PLAT_ARM_GICR_BASE; in bl31_platform_setup()
125 gicr_base = gicv3_driver_data->rdistif_base_addrs[i]; in bl31_platform_setup()
126 gicr_ctlr = gicr_read_ctlr(gicr_base); in bl31_platform_setup()
127 gicr_write_ctlr(gicr_base, gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); in bl31_platform_setup()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_gicv3.c62 .gicr_base = 0x5fe40000,
71 .gicr_base = 0x5fe80000,
80 .gicr_base = 0x5fe80000,
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/
H A Dplat_bl31_setup.c69 ret = mmap_add_dynamic_region(gic_data->gicr_base, in mmap_gic()
70 gic_data->gicr_base, in mmap_gic()
85 .gicr_base = PLAT_GICR_BASE, in bl31_platform_setup()
/rk3399_ARM-atf/plat/arm/board/fvp/fconf/
H A Dfconf_gicv3_config_getter.c49 gicv3_config.gicr_base = addr; in fconf_populate_gicv3_config()
/rk3399_ARM-atf/include/common/
H A Dfdt_fixup.h33 int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base,
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_gicv3.c26 .gicr_base = GICR_BASE,
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_gicv3.c41 tegra_gic_data.gicr_base = TEGRA_GICR_BASE; in tegra_gic_setup()
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_gicv3.c44 .gicr_base = PLAT_BRCM_GICR_BASE,
/rk3399_ARM-atf/drivers/nxp/gic/
H A Dls_gicv3.c26 ls_gic_data.gicr_base = nxp_gicr_addr; in plat_ls_gic_driver_init()
/rk3399_ARM-atf/plat/rockchip/common/
H A Drockchip_gicv3.c40 .gicr_base = PLAT_RK_GICR_BASE,
/rk3399_ARM-atf/common/
H A Dfdt_fixup.c543 uintptr_t gicr_base, unsigned int gicr_frame_size) in fdt_adjust_gic_redist() argument
566 if (gicr_base != INVALID_BASE_ADDR) { in fdt_adjust_gic_redist()
568 reg_32 = cpu_to_fdt32(gicr_base); in fdt_adjust_gic_redist()
571 reg_64 = cpu_to_fdt64(gicr_base); in fdt_adjust_gic_redist()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_gicv3.c61 .gicr_base = PLAT_SQ_GICR_BASE,
/rk3399_ARM-atf/plat/amd/versal2/
H A Dgicv3.c67 .gicr_base = PLAT_GICR_BASE_VALUE,
/rk3399_ARM-atf/plat/arm/board/fvp/include/
H A Dfconf_hw_config_getter.h25 uint64_t gicr_base; member

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