Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpect

fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpected behavior
due to operator precedence and which improves the readibility and
maintainability.

Change-Id: I8d09f136faae2869fc1ef2d6eb46de035b7e6a1e
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(gicv3): do not assume redistributors are powered down" into integration

fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GIC

fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GICR_WAKER.ProcessorSleep bit is set. There is an "assert" in the
GIC setup function to check this.
However when using RESET_TO_BL31, there might be prior firmware running,
and it might have used the GIC already. This is for instance the case on
the Allwinner A523 SoC, where the BootROM initialises the GIC to use it
when handling the built-in USB debug protocol.

Drop the assert, which is not the right thing to do here anyway: it's
not checking an internal state. Instead return early when the
redistributor is already marked as active.
Also keep waiting if ChildrenAsleep is unexpectedly set, but warn about
this.

This fixes booting TF-A on an Allwinner A523 SoC when using the USB
debug mode.

Change-Id: I5be9e1b0489d33b8371fff484e526483d5f3d937
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving inv

fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving invocation of the function after confirming that the
intr_num belongs to SPI range.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I429eb473a7aeccb30309b1ffa5994663393ba0a2

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Merge "fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4" into integration

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions
are received simultaneously from different sources. This hardware issue
impacts NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.

This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.

Erratum documentation:
https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf

The workaround is to ensure that MMIO accesses target the GIC on the
socket that holds the data, for example SPI ranges owned by the socket’s
GIC. This ensures that the GIC will not utilize the inter-socket AXI
Stream interface for servicing these GIC MMIO accesses.

This patch updates the functions that use the GICD_In{E} registers to
ensure that the accesses are directed to the chip that owns the SPI,
instead of using the global alias.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I04e33ba64eb306bd5fdabb56e63cbe273d8cd632

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Merge "fix(gicv3): fixed bug in the initialization of GICv3 SGIs/(E)PPIs interrupt priorities" into integration

fix(gicv3): fixed bug in the initialization of GICv3 SGIs/(E)PPIs interrupt priorities

Default priority was not being set for all interrupts (gicr_write_ipriorityr takes INTID, not register number).

fix(gicv3): fixed bug in the initialization of GICv3 SGIs/(E)PPIs interrupt priorities

Default priority was not being set for all interrupts (gicr_write_ipriorityr takes INTID, not register number). The fix makes the loop to pass INTID in range 0, 4, 8, 12, ...

Signed-off-by: Sylwester Garncarek <sylwester.garncarek@sciopta.com>
Change-Id: Iaa975f6af49f5826c2811161f55242844c28ea81

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Merge "refactor(libc): clean up dependencies in libc" into integration

refactor(libc): clean up dependencies in libc

- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert

refactor(libc): clean up dependencies in libc

- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.

Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568

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Merge changes from topic "mb/gic600-errata" into integration

* changes:
refactor(arm): update BL2 base address
refactor(nxp): use DPG0 mask from Arm GICv3 header
fix(gic600): implement workaro

Merge changes from topic "mb/gic600-errata" into integration

* changes:
refactor(arm): update BL2 base address
refactor(nxp): use DPG0 mask from Arm GICv3 header
fix(gic600): implement workaround to forward highest priority interrupt

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fix(gic600): implement workaround to forward highest priority interrupt

If the interrupt being targeted is released from the CPU before the
CLEAR command is sent to the CPU then a subsequent SET com

fix(gic600): implement workaround to forward highest priority interrupt

If the interrupt being targeted is released from the CPU before the
CLEAR command is sent to the CPU then a subsequent SET command may not
be delivered in a finite time. To workaround this, issue an unblocking
event by toggling GICR_CTLR.DPG* bits after clearing the cpu group
enable (EnableGrp* bits of GIC CPU interface register)
This fix is implemented as per the errata 2384374-part 2 workaround
mentioned here:
https://developer.arm.com/documentation/sden892601/latest/

Change-Id: I13926ceeb7740fa4c05cc5b43170e7ce49598f70
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "arm_fpga_auto" into integration

* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refacto

Merge changes from topic "arm_fpga_auto" into integration

* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file

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feat(gicv3): introduce GIC component identification

The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
i

feat(gicv3): introduce GIC component identification

The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
implementations use certain ID values to identify the distributor, the
redistributors and other parts like ITSes.

Introduce a function that reads those part number IDs, which are spread
over two registers. The actual numbers are only meaningful in connection
with a certain GIC model, which would need to be checked beforehand, by
the caller.

Change-Id: Ia6ff326a1e8b12664e4637bc8e2683d2b5c7721c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at

Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at runtime
refactor(gic): move GIC IIDR numbers
refactor(gicv3): rename GIC Clayton to GIC-700

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feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.

To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.

Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.

Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes Iaf441fe5,I0355ca26 into integration

* changes:
refactor(gicv3): use helper functions to get SPI/ESPI INTID limit
refactor(gicv3): add helper function to get the limit of ESPI INTID

refactor(gicv3): use helper functions to get SPI/ESPI INTID limit

Use helper functions to get SPI and ESPI INTID limit, to remove
several pieces of similar code in gicv3 driver.

Signed-off-by: Heyi

refactor(gicv3): use helper functions to get SPI/ESPI INTID limit

Use helper functions to get SPI and ESPI INTID limit, to remove
several pieces of similar code in gicv3 driver.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iaf441fe5e333c4260e7f6d98df6fdd931591976d

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refactor(gicv3): add helper function to get the limit of ESPI INTID

Add helper function gicv3_get_espi_limit() to get the value of
(maximum extended SPI INTID + 1), so that some duplicated code can

refactor(gicv3): add helper function to get the limit of ESPI INTID

Add helper function gicv3_get_espi_limit() to get the value of
(maximum extended SPI INTID + 1), so that some duplicated code can be
removed later.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I0355ca2647f872e8189add259f6c47d415494cce

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Merge "refactor(gicv3): add helper function to get the limit of SPI INTID" into integration

refactor(gicv3): add helper function to get the limit of SPI INTID

Add helper function gicv3_get_spi_limit() to get the value of (maximum
SPI INTID + 1), so that some duplicated code can be removed

refactor(gicv3): add helper function to get the limit of SPI INTID

Add helper function gicv3_get_spi_limit() to get the value of (maximum
SPI INTID + 1), so that some duplicated code can be removed later.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I160c8a88fbb71d22790b8999a84afbfba766f5e7

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Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration

* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log f

Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration

* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
drivers/gicv3: fix logical issue for num_eints
drivers/gicv3: fix potential GICD context override with ESPI enabled
drivers/gicv3: use mpidr to probe GICR for current CPU

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