1 /* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FCONF_HW_CONFIG_GETTER_H 8 #define FCONF_HW_CONFIG_GETTER_H 9 10 #include <lib/fconf/fconf.h> 11 #include <services/rmm_core_manifest.h> 12 13 #include <plat/arm/common/arm_def.h> 14 15 /* Hardware Config related getter */ 16 #define hw_config__gicv3_config_getter(prop) gicv3_config.prop 17 #define hw_config__topology_getter(prop) soc_topology.prop 18 #define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop 19 #define hw_config__cpu_timer_getter(prop) cpu_timer.prop 20 #define hw_config__dram_layout_getter(prop) dram_layout.prop 21 #define hw_config__pci_props_getter(prop) pci_props.prop 22 23 struct gicv3_config_t { 24 uint64_t gicd_base; 25 uint64_t gicr_base; 26 }; 27 28 struct hw_topology_t { 29 uint32_t plat_cluster_count; 30 uint32_t cluster_cpu_count; 31 uint32_t plat_cpu_count; 32 uint32_t plat_max_pwr_level; 33 }; 34 35 struct uart_serial_config_t { 36 uint64_t uart_base; 37 uint32_t uart_clk; 38 }; 39 40 struct cpu_timer_t { 41 uint32_t clock_freq; 42 }; 43 44 struct dram_layout_t { 45 uint64_t num_banks; 46 struct memory_bank dram_bank[ARM_DRAM_NUM_BANKS]; 47 }; 48 49 struct pci_props_t { 50 uint64_t ecam_base; 51 uint64_t size; 52 uint64_t num_ncoh_regions; 53 struct memory_bank ncoh_regions[ARM_PCI_NUM_REGIONS]; 54 }; 55 56 int fconf_populate_gicv3_config(uintptr_t config); 57 int fconf_populate_topology(uintptr_t config); 58 int fconf_populate_uart_config(uintptr_t config); 59 int fconf_populate_cpu_timer(uintptr_t config); 60 int fconf_populate_dram_layout(uintptr_t config); 61 int fconf_populate_pci_props(uintptr_t config); 62 63 extern struct gicv3_config_t gicv3_config; 64 extern struct hw_topology_t soc_topology; 65 extern struct uart_serial_config_t uart_serial_config; 66 extern struct cpu_timer_t cpu_timer; 67 extern struct dram_layout_t dram_layout; 68 extern struct pci_props_t pci_props; 69 70 #endif /* FCONF_HW_CONFIG_GETTER_H */ 71