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/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
77 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
86 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) argument
87 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) argument
88 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) argument
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H A Daddressmap_shared.h91 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) argument
92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) argument
95 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) argument
96 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) argument
99 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) argument
100 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) argument
102 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) argument
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/dmc/
H A Dsuspend.c73 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
74 #define SYS_REG_DEC_CHINFO_V3(reg2, ch) SYS_REG_DEC_CHINFO(reg2, ch) argument
79 static void exit_low_power(uint32_t ch, struct rk3576_dmc_config *configs) in exit_low_power() argument
82 configs->low_power[ch].pcl_pd = mmio_read_32(DDRPHY_BASE_CH(0) + LP_CON0) & PCL_PD; in exit_low_power()
83 mmio_clrbits_32(DDRPHY_BASE_CH(ch) + LP_CON0, PCL_PD); in exit_low_power()
86 configs->low_power[ch].pwrctl = mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL); in exit_low_power()
87 mmio_clrbits_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, in exit_low_power()
90 while ((mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_STAT) & CTL_OPERATING_MODE_MASK) != in exit_low_power()
95 configs->low_power[ch].grf_ddr_con6 = in exit_low_power()
96 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6)) & 0xff7f; in exit_low_power()
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H A Ddmc_rk3576.h13 #define GRF_CH_CON(ch, n) ((((ch) % 2) * 0x100) + ((n) * 4)) argument
14 #define DDR_GRF_CH_STATUS16(ch) (0x220 + ((ch) * 0x100)) argument
16 #define GRF_DDRPHY_CON0(ch) (0x530 + (((ch) % 2) * 0x4)) argument
/rk3399_ARM-atf/drivers/arm/css/scmi/
H A Dscmi_common.c30 void scmi_get_channel(scmi_channel_t *ch) in scmi_get_channel() argument
32 assert(ch->lock); in scmi_get_channel()
33 scmi_lock_get(ch->lock); in scmi_get_channel()
37 ((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); in scmi_get_channel()
43 void scmi_send_sync_command(scmi_channel_t *ch) in scmi_send_sync_command() argument
45 mailbox_mem_t *mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_send_sync_command()
56 ch->info->ring_doorbell(ch->info); in scmi_send_sync_command()
65 if (ch->info->delay != 0) in scmi_send_sync_command()
66 udelay(ch->info->delay); in scmi_send_sync_command()
80 void scmi_put_channel(scmi_channel_t *ch) in scmi_put_channel() argument
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H A Dscmi_base_proto.c21 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_base_protocol_attributes() local
23 validate_scmi_channel(ch); in scmi_base_protocol_attributes()
25 scmi_get_channel(ch); in scmi_base_protocol_attributes()
27 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_base_protocol_attributes()
33 scmi_send_sync_command(ch); in scmi_base_protocol_attributes()
40 scmi_put_channel(ch); in scmi_base_protocol_attributes()
60 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_base_discover_agent() local
62 validate_scmi_channel(ch); in scmi_base_discover_agent()
64 scmi_get_channel(ch); in scmi_base_discover_agent()
66 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_base_discover_agent()
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H A Dscmi_sys_pwr_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_set() local
25 validate_scmi_channel(ch); in scmi_sys_pwr_state_set()
27 scmi_get_channel(ch); in scmi_sys_pwr_state_set()
29 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_sys_pwr_state_set()
36 scmi_send_sync_command(ch); in scmi_sys_pwr_state_set()
43 scmi_put_channel(ch); in scmi_sys_pwr_state_set()
56 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_get() local
58 validate_scmi_channel(ch); in scmi_sys_pwr_state_get()
60 scmi_get_channel(ch); in scmi_sys_pwr_state_get()
62 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_sys_pwr_state_get()
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H A Dscmi_pwr_dmn_proto.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_set() local
32 validate_scmi_channel(ch); in scmi_pwr_state_set()
34 scmi_get_channel(ch); in scmi_pwr_state_set()
36 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_pwr_state_set()
44 scmi_send_sync_command(ch); in scmi_pwr_state_set()
51 scmi_put_channel(ch); in scmi_pwr_state_set()
65 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_get() local
67 validate_scmi_channel(ch); in scmi_pwr_state_get()
69 scmi_get_channel(ch); in scmi_pwr_state_get()
71 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_pwr_state_get()
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H A Dscmi_ap_core_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_set_reset_addr() local
25 validate_scmi_channel(ch); in scmi_ap_core_set_reset_addr()
27 scmi_get_channel(ch); in scmi_ap_core_set_reset_addr()
29 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_ap_core_set_reset_addr()
37 scmi_send_sync_command(ch); in scmi_ap_core_set_reset_addr()
44 scmi_put_channel(ch); in scmi_ap_core_set_reset_addr()
57 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_get_reset_addr() local
60 validate_scmi_channel(ch); in scmi_ap_core_get_reset_addr()
62 scmi_get_channel(ch); in scmi_ap_core_get_reset_addr()
64 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_ap_core_get_reset_addr()
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H A Dscmi_private.h155 void scmi_get_channel(scmi_channel_t *ch);
156 void scmi_send_sync_command(scmi_channel_t *ch);
157 void scmi_put_channel(scmi_channel_t *ch);
159 static inline void validate_scmi_channel(scmi_channel_t *ch) in validate_scmi_channel() argument
161 assert(ch && ch->is_initialized); in validate_scmi_channel()
162 assert(ch->info && ch->info->scmi_mbx_mem); in validate_scmi_channel()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
28 ((n) << (8 + (ch) * 4)))
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
30 ((n) << (9 + (ch) * 4)))
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) in phy_pctrl_reset() argument
138 rkclk_ddr_reset(ch, 1, 1); in phy_pctrl_reset()
140 rkclk_ddr_reset(ch, 1, 0); in phy_pctrl_reset()
142 rkclk_ddr_reset(ch, 0, 0); in phy_pctrl_reset()
146 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) in set_cs_training_index() argument
152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
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H A Ddram.c26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init() local
27 struct rk3399_msch_timings *noc = &ch->noc_timings; in dram_init()
32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); in dram_init()
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); in dram_init()
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); in dram_init()
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); in dram_init()
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); in dram_init()
38 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); in dram_init()
39 ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); in dram_init()
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/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram.c246 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
248 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
249 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
253 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
268 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
318 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
319 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
326 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
327 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
342 #define foreach_vch(ch) \ argument
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H A Dboot_init_dram_regdef.h31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
64 #define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) argument
/rk3399_ARM-atf/drivers/nxp/scmi/vendor/
H A Dscmi_imx9.c24 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_core_set_reset_addr() local
26 validate_scmi_channel(ch); in scmi_core_set_reset_addr()
28 scmi_get_channel(ch); in scmi_core_set_reset_addr()
30 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_core_set_reset_addr()
38 scmi_send_sync_command(ch); in scmi_core_set_reset_addr()
45 scmi_put_channel(ch); in scmi_core_set_reset_addr()
55 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_core_start() local
57 validate_scmi_channel(ch); in scmi_core_start()
59 scmi_get_channel(ch); in scmi_core_start()
61 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_core_start()
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/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp/
H A Dbpmp.c24 static uint32_t channel_field(unsigned int ch) in channel_field() argument
26 return mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET) & CH_MASK(ch); in channel_field()
29 static bool master_free(unsigned int ch) in master_free() argument
31 return channel_field(ch) == MA_FREE(ch); in master_free()
34 static bool master_acked(unsigned int ch) in master_acked() argument
36 return channel_field(ch) == MA_ACKD(ch); in master_acked()
39 static void signal_slave(unsigned int ch) in signal_slave() argument
41 mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET, CH_MASK(ch)); in signal_slave()
44 static void free_master(unsigned int ch) in free_master() argument
47 MA_ACKD(ch) ^ MA_FREE(ch)); in free_master()
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/rk3399_ARM-atf/drivers/renesas/common/
H A Dddr_regs.h16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
96 #define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) argument
101 #define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) argument
106 #define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) argument
111 #define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) argument
116 #define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) argument
121 #define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) argument
126 #define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) argument
131 #define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) argument
132 #define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) argument
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/rk3399_ARM-atf/drivers/arm/css/scmi/vendor/
H A Dscmi_sq.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_get_draminfo() local
33 validate_scmi_channel(ch); in scmi_get_draminfo()
35 scmi_get_channel(ch); in scmi_get_draminfo()
37 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_get_draminfo()
43 scmi_send_sync_command(ch); in scmi_get_draminfo()
57 scmi_put_channel(ch); in scmi_get_draminfo()
/rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/
H A Dbpmp.h22 #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
23 #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) argument
24 #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
/rk3399_ARM-atf/lib/libc/
H A Dprintf.c189 char ch = *fmt; in vprintf() local
190 if ((ch < '0') || (ch > '9')) { in vprintf()
193 padn = (padn * 10) + (ch - '0'); in vprintf()
210 char ch = *fmt; in vprintf() local
211 if ((ch < '0') || (ch > '9')) { in vprintf()
214 padn = (padn * 10) + (ch - '0'); in vprintf()
H A Dstrchr.c41 strchr(const char *p, int ch) in strchr() argument
45 c = ch; in strchr()
H A Dstrrchr.c36 strrchr(const char *p, int ch) in strrchr() argument
41 c = ch; in strrchr()
/rk3399_ARM-atf/services/spd/trusty/
H A Dgeneric-arm64-smcall.c40 static void trusty_dputc(char ch, int secure) in trusty_dputc() argument
48 s->linebuf[s->l++] = ch; in trusty_dputc()
49 if (s->l == sizeof(s->linebuf) || ch == '\n') { in trusty_dputc()
57 if (ch != '\n') { in trusty_dputc()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp_ipc/
H A Divc.c75 volatile const struct ivc_channel_header *ch) in ivc_channel_empty() argument
82 uint32_t wr_count = ch->w_count; in ivc_channel_empty()
83 uint32_t rd_count = ch->r_count; in ivc_channel_empty()
106 volatile const struct ivc_channel_header *ch) in ivc_channel_full() argument
108 uint32_t wr_count = ch->w_count; in ivc_channel_full()
109 uint32_t rd_count = ch->r_count; in ivc_channel_full()
121 volatile const struct ivc_channel_header *ch) in ivc_channel_avail_count() argument
123 uint32_t wr_count = ch->w_count; in ivc_channel_avail_count()
124 uint32_t rd_count = ch->r_count; in ivc_channel_avail_count()
222 volatile const struct ivc_channel_header *ch, in ivc_frame_pointer() argument
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/rk3399_ARM-atf/drivers/arm/mhu/
H A Dmhu_wrapper_v3_x.c178 uint32_t ch; in mhu_init_sender() local
209 for (ch = 0; ch < num_ch; ch++) { in mhu_init_sender()
211 dev, ch, MHU_V3_X_CHANNEL_TYPE_DBCH); in mhu_init_sender()
224 uint32_t ch; in mhu_init_receiver() local
249 for (ch = 0; ch < (num_ch - 1); ch++) { in mhu_init_receiver()
251 err = mhu_v3_x_doorbell_mask_set(dev, ch, UINT32_MAX); in mhu_init_receiver()

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