| #
d6b458e8 |
| 24-Oct-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Ia66dd232,Ie0ddbe0b,Idd191614 into integration
* changes:
fix(rcar3-drivers): update DDR setting
fix(rcar3): fix CPG register code comment
fix(rcar3): update Draak and Eagle boar
Merge changes Ia66dd232,Ie0ddbe0b,Idd191614 into integration
* changes:
fix(rcar3-drivers): update DDR setting
fix(rcar3): fix CPG register code comment
fix(rcar3): update Draak and Eagle board IDs
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| #
138ddcbf |
| 22-Jul-2022 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
fix(rcar3-drivers): update DDR setting
Update R-Car H3/M3/M3N DDR setting rev.0.42.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ia66dd2329ab3a3ca39132a737e92b3a4864
fix(rcar3-drivers): update DDR setting
Update R-Car H3/M3/M3N DDR setting rev.0.42.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ia66dd2329ab3a3ca39132a737e92b3a4864db02d
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| #
c87f2c1d |
| 13-Aug-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM siz
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM size setting for M3N
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
feat(drivers/rcar3): ddr: add function to judge a DDR rank
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
fix(drivers/rcar3): fix CPG registers redefinition
fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
refactor(plat/rcar3): factor out DT memory node generation
feat(plat/rcar3): add optional support for gzip-compressed BL33
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| #
ec767c1b |
| 30-Oct-2020 |
Chiaki Fujii <chiaki.fujii.wj@renesas.com> |
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi H
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
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| #
e9cd36f5 |
| 21-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration
* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add
Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration
* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add support for RZ/G2E
drivers: renesas: rzg: Add QoS support for RZ/G2E
drivers: renesas: rzg: Add PFC support for RZ/G2E
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
drivers: renesas: rzg: Add QoS support for RZ/G2N
drivers: renesas: rzg: Add PFC support for RZ/G2N
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
drivers: renesas: rzg: Add QoS support for RZ/G2H
drivers: renesas: rzg: Add PFC support for RZ/G2H
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
drivers: renesas: rzg: Switch using common ddr code
drivers: renesas: ddr: Move to common
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| #
b939cbbb |
| 19-Apr-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
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| #
fe5929c1 |
| 19-Apr-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
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| #
778db0e9 |
| 10-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.r
drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
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| #
faf5587c |
| 09-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.
drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
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|