Lines Matching refs:ch
73 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
74 #define SYS_REG_DEC_CHINFO_V3(reg2, ch) SYS_REG_DEC_CHINFO(reg2, ch) argument
79 static void exit_low_power(uint32_t ch, struct rk3576_dmc_config *configs) in exit_low_power() argument
82 configs->low_power[ch].pcl_pd = mmio_read_32(DDRPHY_BASE_CH(0) + LP_CON0) & PCL_PD; in exit_low_power()
83 mmio_clrbits_32(DDRPHY_BASE_CH(ch) + LP_CON0, PCL_PD); in exit_low_power()
86 configs->low_power[ch].pwrctl = mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL); in exit_low_power()
87 mmio_clrbits_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, in exit_low_power()
90 while ((mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_STAT) & CTL_OPERATING_MODE_MASK) != in exit_low_power()
95 configs->low_power[ch].grf_ddr_con6 = in exit_low_power()
96 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6)) & 0xff7f; in exit_low_power()
97 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6), (0x1ul << (15 + 16))); in exit_low_power()
100 configs->low_power[ch].grf_ddr_con0 = in exit_low_power()
101 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0)) & 0x1f00; in exit_low_power()
102 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0), 0x1f000000); in exit_low_power()
109 configs->low_power[ch].grf_ddr_con1 = in exit_low_power()
110 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1)) & 0x90e6; in exit_low_power()
111 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1), 0x90e60000); in exit_low_power()
113 configs->low_power[ch].hwlp_0 = mmio_read_32(HWLP_BASE_CH(ch) + 0x0); in exit_low_power()
114 mmio_write_32(HWLP_BASE_CH(ch) + 0x0, 0x0); in exit_low_power()
115 configs->low_power[ch].hwlp_c = mmio_read_32(HWLP_BASE_CH(ch) + 0xc); in exit_low_power()
116 mmio_write_32(HWLP_BASE_CH(ch) + 0xc, 0x0); in exit_low_power()
119 configs->low_power[ch].grf_ddrphy_con0 = in exit_low_power()
120 mmio_read_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch)) & BIT(14); in exit_low_power()
121 mmio_write_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch), BIT(14 + 16)); in exit_low_power()
124 configs->low_power[ch].clkgatectl = in exit_low_power()
125 mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL) & 0x3f; in exit_low_power()
127 configs->low_power[ch].dfi_lp_mode_apb = in exit_low_power()
128 (mmio_read_32(DDRPHY_BASE_CH(ch) + DFI_LP_CON0) >> 31) & 0x1; in exit_low_power()
131 static void resume_low_power(uint32_t ch, struct rk3576_dmc_config *configs) in resume_low_power() argument
134 if (configs->low_power[ch].dfi_lp_mode_apb != 0) in resume_low_power()
135 mmio_setbits_32(DDRPHY_BASE_CH(ch) + DFI_LP_CON0, DFI_LP_MODE_APB); in resume_low_power()
138 mmio_clrsetbits_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL, in resume_low_power()
139 0x3f, configs->low_power[ch].clkgatectl & 0x3f); in resume_low_power()
142 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6), in resume_low_power()
143 (0xff7ful << 16) | configs->low_power[ch].grf_ddr_con6); in resume_low_power()
145 mmio_write_32(HWLP_BASE_CH(ch) + 0xc, configs->low_power[ch].hwlp_c); in resume_low_power()
146 mmio_write_32(HWLP_BASE_CH(ch) + 0x0, configs->low_power[ch].hwlp_0); in resume_low_power()
149 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0), in resume_low_power()
150 (0x1f00ul << 16) | configs->low_power[ch].grf_ddr_con0); in resume_low_power()
157 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1), in resume_low_power()
158 (0x90e6ul << 16) | configs->low_power[ch].grf_ddr_con1); in resume_low_power()
161 mmio_write_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch), in resume_low_power()
162 BIT(14 + 16) | configs->low_power[ch].grf_ddrphy_con0); in resume_low_power()
165 mmio_write_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, configs->low_power[ch].pwrctl); in resume_low_power()
168 if (configs->low_power[ch].pcl_pd != 0) in resume_low_power()
169 mmio_setbits_32(DDRPHY_BASE_CH(ch) + LP_CON0, PCL_PD); in resume_low_power()