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Searched refs:PLAT_PRI_BITS (Results 1 – 16 of 16) sorted by relevance

/rk3399_ARM-atf/plat/common/aarch64/
H A Dplat_ehf.c17 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_RAS_PRI),
22 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
25 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
31 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
34 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
45 EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions), PLAT_PRI_BITS);
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dzynqmp_ehf.c17 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
20 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
24 EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS);
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_ehf.c14 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
17 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
22 EHF_REGISTER_PRIORITIES(imx_exceptions, ARRAY_SIZE(imx_exceptions), PLAT_PRI_BITS);
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_spm.c73 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
75 EHF_REGISTER_PRIORITIES(sq_exceptions, ARRAY_SIZE(sq_exceptions), PLAT_PRI_BITS);
/rk3399_ARM-atf/plat/nvidia/tegra/include/
H A Dplatform_def.h94 #define PLAT_PRI_BITS U(3) macro
100 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS,\
/rk3399_ARM-atf/plat/xilinx/versal_net/include/
H A Dplatform_def.h132 #define PLAT_PRI_BITS U(3) macro
135 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_IPI_PRI)
/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dplatform_def.h126 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/plat/socionext/synquacer/include/
H A Dplatform_def.h174 #define PLAT_PRI_BITS 2 macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/
H A Dplatform_def.h37 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/
H A Dplatform_def.h38 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/
H A Dnrd_plat_arm_def2.h239 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/
H A Dplatform_def.h59 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/plat/qemu/qemu/include/
H A Dplatform_def.h299 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_plat_arm_def3.h244 #define PLAT_PRI_BITS U(3) macro
/rk3399_ARM-atf/docs/components/
H A Dexception-handling.rst310 #define PLAT_PRI_BITS 2
320 EHF_PRI_DESC(PLAT_PRI_BITS, DISP1_PRIO),
321 EHF_PRI_DESC(PLAT_PRI_BITS, DISP2_PRIO),
322 EHF_PRI_DESC(PLAT_PRI_BITS, DISP3_PRIO),
327 PLAT_PRI_BITS);
/rk3399_ARM-atf/include/plat/arm/common/
H A Darm_def.h806 #define PLAT_PRI_BITS 3 macro