| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi | 30 DIV_CFG(DIV_LSMCU, 1)
31 DIV_CFG(DIV_APB1, 0)
32 DIV_CFG(DIV_APB2, 0)
33 DIV_CFG(DIV_APB3, 0)
34 DIV_CFG(DIV_APB4, 0)
35 DIV_CFG(DIV_APBDBG, 0)
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| H A D | stm32mp257f-dk-ca35tdcid-rcc.dtsi | 35 DIV_CFG(DIV_LSMCU, 1)
36 DIV_CFG(DIV_APB1, 0)
37 DIV_CFG(DIV_APB2, 0)
38 DIV_CFG(DIV_APB3, 0)
39 DIV_CFG(DIV_APB4, 0)
40 DIV_CFG(DIV_APBDBG, 0)
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| H A D | stm32mp257f-ev1-ca35tdcid-rcc.dtsi | 35 DIV_CFG(DIV_LSMCU, 1)
36 DIV_CFG(DIV_APB1, 0)
37 DIV_CFG(DIV_APB2, 0)
38 DIV_CFG(DIV_APB3, 0)
39 DIV_CFG(DIV_APB4, 0)
40 DIV_CFG(DIV_APBDBG, 0)
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32mp13.c | 777 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ macro
787 DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
788 DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
789 DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
790 DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
791 DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
792 DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
793 DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
794 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
795 DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
[all …]
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| H A D | stm32mp1_clk.c | 123 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\ macro
132 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31),
133 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 31),
134 DIV_CFG(DIV_MCU, RCC_MCUDIVR, 0, 4, 31),
135 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 31),
136 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 31),
137 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 31),
138 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 31),
139 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31),
140 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, DIV_NO_BIT_RDY),
[all …]
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| H A D | clk-stm32mp2.c | 613 #undef DIV_CFG
614 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ macro
624 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
625 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
626 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
627 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
629 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
631 DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
632 DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
633 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
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| /rk3399_ARM-atf/include/dt-bindings/clock/ |
| H A D | stm32mp21-clksrc.h | 69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ macro
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| H A D | stm32mp25-clksrc.h | 69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ macro
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