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Searched refs:CTX_SPSR_EL3 (Results 1 – 14 of 14) sorted by relevance

/rk3399_ARM-atf/bl31/
H A Dbl31_traps.c236 u_register_t old_spsr = read_ctx_reg(state, CTX_SPSR_EL3); in inject_undef64()
245 write_ctx_reg(state, CTX_SPSR_EL3, new_spsr); in inject_undef64()
268 write_ctx_reg(state, CTX_SPSR_EL3, new_spsr); in inject_undef64()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_fiq_glue.c67 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); in tegra_fiq_interrupt_handler()
/rk3399_ARM-atf/services/std_svc/drtm/
H A Ddrtm_main.c188 uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in drtm_dl_check_caller_el()
578 uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3); in drtm_dl_reset_dlme_context()
600 write_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3, spsr_el3); in drtm_dl_reset_dlme_context()
607 uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in drtm_dl_prepare_eret_to_dlme()
/rk3399_ARM-atf/plat/arm/common/aarch64/
H A Dexecution_state_switch.c61 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch()
/rk3399_ARM-atf/services/spd/trusty/
H A Dtrusty.c165 ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); in trusty_fiq_handler()
186 ctx->fiq_handler_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); in trusty_set_fiq_handler()
317 CTX_SPSR_EL3)); in trusty_init()
/rk3399_ARM-atf/services/spd/tspd/
H A Dtspd_main.c194 CTX_SPSR_EL3); in tspd_sel1_interrupt_handler()
392 CTX_SPSR_EL3, in tspd_smc_handler()
/rk3399_ARM-atf/services/std_svc/sdei/
H A Dsdei_intr_mgmt.c187 disp_ctx->spsr_el3 = read_ctx_reg(tgt_el3, CTX_SPSR_EL3); in save_event_ctx()
207 write_ctx_reg(tgt_el3, CTX_SPSR_EL3, disp_ctx->spsr_el3); in restore_event_ctx()
/rk3399_ARM-atf/bl31/aarch64/
H A Dea_delegate.S251 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
H A Druntime_exceptions.S369 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
538 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
/rk3399_ARM-atf/bl1/aarch64/
H A Dbl1_exceptions.S261 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
/rk3399_ARM-atf/plat/qti/qtiseclib/src/
H A Dqtiseclib_cb_interface.c141 read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in qtiseclib_cb_get_ns_ctx()
/rk3399_ARM-atf/include/lib/el3_runtime/aarch64/
H A Dcontext.h80 #define CTX_SPSR_EL3 U(0x10) macro
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext_mgmt.c569 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); in setup_context_common()
2030 write_ctx_reg(state, CTX_SPSR_EL3, spsr); in cm_set_elr_spsr_el3()
H A Dcontext.S634 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]