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Searched refs:BITS_WITH_WMASK (Results 1 – 25 of 27) sorted by relevance

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/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dm0_ctl.c38 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); in m0_init()
47 BITS_WITH_WMASK((addr >> 12) & 0xffff, in m0_configure_execute_addr()
50 BITS_WITH_WMASK((addr >> 28) & 0xf, in m0_configure_execute_addr()
58 BITS_WITH_WMASK(0x0, 0xf, 0)); in m0_start()
65 BITS_WITH_WMASK(0x0, 0x4, 0)); in m0_start()
70 BITS_WITH_WMASK(0x0, 0x20, 0)); in m0_start()
78 BITS_WITH_WMASK(0x24, 0x24, 0)); in m0_stop()
82 BITS_WITH_WMASK(0xf, 0xf, 0)); in m0_stop()
H A Dpmu.h50 #define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0)
51 #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12)
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift)
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift)
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift)
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift)
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift)
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift)
67 #define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0)
68 #define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0)
69 #define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0)
83 #define CPUL_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 14)
[all …]
H A Drk3588_rstd.c37 BITS_WITH_WMASK(assert_not_deassert, 0x1U, offset)); in rk3588_reset_explicit()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pwm/
H A Dpwm.c38 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
47 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
56 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
65 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
97 val = BITS_WITH_WMASK(PMUGRF_GPIO0A6_IOMUX_PWM, in enable_pwms()
104 val = BITS_WITH_WMASK(PMUGRF_GPIO1C3_IOMUX_PWM, in enable_pwms()
111 val = BITS_WITH_WMASK(GRF_GPIO4C6_IOMUX_PWM, in enable_pwms()
118 val = BITS_WITH_WMASK(GRF_GPIO4C2_IOMUX_PWM, in enable_pwms()
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift)
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift)
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift)
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift)
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift)
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift)
67 #define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0)
68 #define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0)
69 #define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0)
79 #define CPUL_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 12)
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h51 #define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15)
52 #define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15)
55 BITS_WITH_WMASK(0, 0x1, 1) : \
56 BITS_WITH_WMASK(0, 0x1, ((id) * 4))
58 BITS_WITH_WMASK(1, 0x1, 1) : \
59 BITS_WITH_WMASK(1, 0x1, ((id) * 4))
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c287 BITS_WITH_WMASK(1U, 1U, 15)); in pll_pwr_dwn()
290 BITS_WITH_WMASK(1, 1, 14)); in pll_pwr_dwn()
293 BITS_WITH_WMASK(0, 1, 14)); in pll_pwr_dwn()
308 BITS_WITH_WMASK(1U, 1U, 15)); in dpll_suspend()
310 BITS_WITH_WMASK(1, 1, 14)); in dpll_suspend()
318 BITS_WITH_WMASK(1U, 1U, 15)); in dpll_resume()
320 BITS_WITH_WMASK(0, 1, 14)); in dpll_resume()
384 BITS_WITH_WMASK(0, 0x1f, 0)); in pm_plls_suspend()
388 BITS_WITH_WMASK(0, 0xf, 0)); in pm_plls_suspend()
392 BITS_WITH_WMASK(0, 0x1f, 0)); in pm_plls_suspend()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dsecure.c34 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 4)); in secure_init()
35 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 5)); in secure_init()
38 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(1), BITS_WITH_WMASK(1, 0x1, 14)); in secure_init()
/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Drockchip_common_clock.c89 BITS_WITH_WMASK(div - 1, div_mask, in clk_scmi_common_set_rate()
103 BITS_WITH_WMASK(best_sel, sel_mask, in clk_scmi_common_set_rate()
124 BITS_WITH_WMASK(div_mask, div_mask, in clk_scmi_common_set_rate()
127 BITS_WITH_WMASK(best_sel, sel_mask, in clk_scmi_common_set_rate()
130 BITS_WITH_WMASK(best_div - 1, div_mask, in clk_scmi_common_set_rate()
139 BITS_WITH_WMASK(!status, 0x1U, in clk_scmi_common_set_status()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c95 BITS_WITH_WMASK(pd_state, 0x1, 0)); in cpu_power_domain_ctr()
151 BITS_WITH_WMASK(0, 0xf, 0)); in cpus_power_domain_on()
164 BITS_WITH_WMASK(1, 0x1, pmu_cpu_pm_sft_wakeup_en)); in cpus_power_domain_on()
184 BITS_WITH_WMASK(0, 0xf, 0)); in cpus_power_domain_off()
198 BITS_WITH_WMASK(core_pm_value, 0xf, 0)); in cpus_power_domain_off()
234 BITS_WITH_WMASK(0, 0xf, 0)); in rockchip_soc_cores_pwr_dm_on_finish()
260 BITS_WITH_WMASK(0, 0xf, 0)); in rockchip_soc_cores_pwr_dm_resume()
291 BITS_WITH_WMASK(0x77, 0xff, 4)); in ddr_resume()
407 BITS_WITH_WMASK(state, 0x1, bus % 16)); in pmu_bus_idle_req()
435 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); in pmu_power_domain_ctr()
[all …]
H A Dpm_pd_regs.c377 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); in pd_bcore_restore()
379 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); in pd_bcore_restore()
413 mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); in pd_core_restore()
414 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); in pd_core_restore()
416 mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); in pd_core_restore()
417 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); in pd_core_restore()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/
H A Dsecure.h22 #define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
23 #define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c142 mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4)); in ddr_resume()
254 BITS_WITH_WMASK(state, 0x1, bus % 16)); in pmu_bus_idle_req()
277 BITS_WITH_WMASK(state, msk, 0)); in pmu_qch_pwr_ctlr()
423 BITS_WITH_WMASK(pmu_pd_off, 0x1, pd % 16)); in pmu_power_domain_reset_mem()
438 BITS_WITH_WMASK(pmu_pd_on, 0x1, pd % 16)); in pmu_power_domain_reset_mem()
475 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); in pmu_power_domain_ctr()
734 BITS_WITH_WMASK(0, 0x1, core_pm_en)); in cpus_power_domain_on()
736 BITS_WITH_WMASK(1, 0x1, core_pm_sft_wakeup_en)); in cpus_power_domain_on()
750 BITS_WITH_WMASK(apm_value, 0x3, 0)); in cpus_power_domain_off()
779 mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); in nonboot_cpus_off()
[all …]
H A Dpm_pd_regs.c488 BITS_WITH_WMASK(2, 0x3, 0)); in pd_dsu_core_restore()
490 BITS_WITH_WMASK(2, 0x3, 0)); in pd_dsu_core_restore()
500 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(1, 0x1, 14)); in pd_dsu_core_restore()
501 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); in pd_dsu_core_restore()
502 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); in pd_dsu_core_restore()
503 mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); in pd_dsu_core_restore()
505 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(0, 0x1, 14)); in pd_dsu_core_restore()
506 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); in pd_dsu_core_restore()
507 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); in pd_dsu_core_restore()
508 mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); in pd_dsu_core_restore()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c139 BITS_WITH_WMASK(pd_state, 0x1, pd)); in pmu_power_domain_ctr()
168 BITS_WITH_WMASK(state, 0x1, bus)); in pmu_bus_idle_req()
589 BITS_WITH_WMASK(0, 0x3, pgrf_pvtm_st)); in pvtm_32k_config()
592 BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_en)); in pvtm_32k_config()
598 BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_st)); in pvtm_32k_config()
626 BITS_WITH_WMASK(pvtm_div, 0x3f, pgrf_pvtm_div)); in pvtm_32k_config()
630 BITS_WITH_WMASK(1, 0x3U, 14)); in pvtm_32k_config()
648 mmio_write_32(DDR_UPCTL_BASE + 0x30, BITS_WITH_WMASK(0x0, 0x3, 0)); in ddr_sleep_config()
652 mmio_write_32(DDRGRF_BASE + 0x4, BITS_WITH_WMASK(0x0, 0x1f, 0)); in ddr_sleep_config()
656 mmio_write_32(DDR_STDBY_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 0)); in ddr_sleep_config()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c32 #define CLKDIV_5BITS_SHF0(div) BITS_WITH_WMASK(div, 0x1f, 0)
33 #define CLKDIV_5BITS_SHF8(div) BITS_WITH_WMASK(div, 0x1f, 8)
35 #define CLKDIV_4BITS_SHF0(div) BITS_WITH_WMASK(div, 0xf, 0)
36 #define CLKDIV_2BITS_SHF4(div) BITS_WITH_WMASK(div, 0x3, 4)
67 #define SCLK_PATH_NOR_APLL (BITS_WITH_WMASK(0, 0x3, 8) | WMSK_BIT(15))
68 #define SCLK_PATH_NOR_GPLL (BITS_WITH_WMASK(0x1, 0x3, 8) | WMSK_BIT(15))
69 #define SCLK_PATH_NOR_NPLL BITS_WITH_WMASK(0x2, 0x3, 8) | WMSK_BIT(15)
101 #define GPU_CLK_PATH_NOR_MPLL (WMSK_BIT(11) | BITS_WITH_WMASK(0, 0x3, 6))
102 #define GPU_CLK_PATH_NOR_GPLL (WMSK_BIT(11) | BITS_WITH_WMASK(0x1, 0x3, 6))
103 #define GPU_CLK_PATH_NOR_CPLL (WMSK_BIT(11) | BITS_WITH_WMASK(0x2, 0x3, 6))
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.c51 BITS_WITH_WMASK(2, 0x3, 2)); in clear_glb_reset_status()
128 BITS_WITH_WMASK(0x77, 0xff, 4)); in plat_rockchip_soc_init()
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c67 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_ADDR_WMSK, 0)); in sgrf_ddr_rgn_config()
71 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_ADDR_WMSK, 0)); in sgrf_ddr_rgn_config()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.c75 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); in sgrf_ddr_rgn_config()
79 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); in sgrf_ddr_rgn_config()
/rk3399_ARM-atf/plat/rockchip/common/include/
H A Dplat_private.h58 #ifndef BITS_WITH_WMASK
59 #define BITS_WITH_WMASK(bits, msk, shift)\ macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c161 BITS_WITH_WMASK(0, 1, info->clkgate_bit) in gpio_get_clock()
175 mmio_write_32(info->clkgate_reg, BITS_WITH_WMASK(1, 1, info->clkgate_bit)); in gpio_put_clock()
216 BITS_WITH_WMASK(val, GPIO_P_MASK, id * 2) in set_pull()
317 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT)); in plat_rockchip_save_gpio()
369 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT)); in plat_rockchip_restore_gpio()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h35 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
38 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/
H A Dotp.c183 BITS_WITH_WMASK(0x2, 0xffu, SBPI_DEV_ID_SHIFT)); /* device id */ in rk_otp_ecc_enable()
237 BITS_WITH_WMASK(0x2, 0xffu, SBPI_DEV_ID_SHIFT)); /* device id */ in rk_otp_sbpi_read()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c425 BITS_WITH_WMASK(apm_value, 0xf, offset)); in cpus_power_domain_off()
481 BITS_WITH_WMASK(0, 0xf, offset)); in rockchip_soc_cores_pwr_dm_on_finish()

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