95 		      BITS_WITH_WMASK(pd_state, 0x1, 0));  in cpu_power_domain_ctr()
151 			      BITS_WITH_WMASK(0, 0xf, 0));  in cpus_power_domain_on()
164 			      BITS_WITH_WMASK(1, 0x1, pmu_cpu_pm_sft_wakeup_en));  in cpus_power_domain_on()
184 			      BITS_WITH_WMASK(0, 0xf, 0));  in cpus_power_domain_off()
198 			      BITS_WITH_WMASK(core_pm_value, 0xf, 0));  in cpus_power_domain_off()
234 		      BITS_WITH_WMASK(0, 0xf, 0));  in rockchip_soc_cores_pwr_dm_on_finish()
260 		      BITS_WITH_WMASK(0, 0xf, 0));  in rockchip_soc_cores_pwr_dm_resume()
291 		      BITS_WITH_WMASK(0x77, 0xff, 4));  in ddr_resume()
407 		      BITS_WITH_WMASK(state, 0x1, bus % 16));  in pmu_bus_idle_req()
435 		      BITS_WITH_WMASK(pd_state, 0x1, pd % 16));  in pmu_power_domain_ctr()
603 		      BITS_WITH_WMASK(0x7, 0xf, 0));  in sleep_pin_config()
605 		      BITS_WITH_WMASK(0, 0x1, 7));  in sleep_pin_config()
607 		      BITS_WITH_WMASK(9, 0xfu, 12));  in sleep_pin_config()
637 		      BITS_WITH_WMASK(0, 0xf, 4));  in pmu_sleep_config()
696 		      BITS_WITH_WMASK(key_upd_msk, 0x7, 8));  in pmu_sleep_config()
698 		      BITS_WITH_WMASK(fw_lkp_upd_msk, 0x7, 10));  in pmu_sleep_config()
700 		      BITS_WITH_WMASK(fw_ddr_upd_msk, 0x7u, 13));  in pmu_sleep_config()
785 		      BITS_WITH_WMASK(0x9, 0x9, 2));  in pmu_sleep_config()
839 		      BITS_WITH_WMASK(1, 0x1, 14));  in secure_watchdog_disable()
902 		      BITS_WITH_WMASK(0x3, 0x3, 2));  in pm_pll_suspend()
997 		      BITS_WITH_WMASK(1, 0x1, 3));  in rockchip_soc_system_off()
1001 		      BITS_WITH_WMASK(1, 0x1, 3));  in rockchip_soc_system_off()
1018 		      BITS_WITH_WMASK(0xf, 0xf, 6));  in rockchip_pmu_pd_repair_init()
1045 	mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(2), BITS_WITH_WMASK(1, 0x3, 0));  in plat_rockchip_pmu_init()
1049 		      BITS_WITH_WMASK(0x1, 0x1, 0));  in plat_rockchip_pmu_init()