Lines Matching refs:BITS_WITH_WMASK
139 BITS_WITH_WMASK(pd_state, 0x1, pd)); in pmu_power_domain_ctr()
168 BITS_WITH_WMASK(state, 0x1, bus)); in pmu_bus_idle_req()
589 BITS_WITH_WMASK(0, 0x3, pgrf_pvtm_st)); in pvtm_32k_config()
592 BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_en)); in pvtm_32k_config()
598 BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_st)); in pvtm_32k_config()
626 BITS_WITH_WMASK(pvtm_div, 0x3f, pgrf_pvtm_div)); in pvtm_32k_config()
630 BITS_WITH_WMASK(1, 0x3U, 14)); in pvtm_32k_config()
648 mmio_write_32(DDR_UPCTL_BASE + 0x30, BITS_WITH_WMASK(0x0, 0x3, 0)); in ddr_sleep_config()
652 mmio_write_32(DDRGRF_BASE + 0x4, BITS_WITH_WMASK(0x0, 0x1f, 0)); in ddr_sleep_config()
656 mmio_write_32(DDR_STDBY_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 0)); in ddr_sleep_config()
662 mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 5)); in ddr_sleep_config()
664 mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x1, 0x1, 4)); in ddr_sleep_config()
670 BITS_WITH_WMASK(0x0, 0x1, 12)); in ddr_sleep_config()
754 BITS_WITH_WMASK(1, 0x3, 8)); in pmu_sleep_config()
872 uint32_t val = BITS_WITH_WMASK(mode, 0x3, PLL_MODE_SHIFT(pll_id)); in pll_set_mode()
878 BITS_WITH_WMASK(mode, 0x3, 0)); in pll_set_mode()
932 BITS_WITH_WMASK(0, 0xf, 0)); in pm_plls_suspend()
936 BITS_WITH_WMASK(0, 0xf, 8)); in pm_plls_suspend()
1012 mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX, BITS_WITH_WMASK(0, 0x3, 8)); in rockchip_soc_system_off()
1059 BITS_WITH_WMASK(1, 0x1, 13)); in plat_rockchip_pmu_init()