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Searched refs:set_rate (Results 1 – 17 of 17) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dat91_cpu_opp.c60 return clk->parent->ops->set_rate(clk->parent, rate, parent_rate); in cpu_opp_clk_set_rate()
64 .set_rate = cpu_opp_clk_set_rate,
H A Dat91_audio_pll.c281 .set_rate = clk_audio_pll_frac_set_rate,
288 .set_rate = clk_audio_pll_pad_set_rate,
295 .set_rate = clk_audio_pll_pmc_set_rate,
H A Dat91_plldiv.c43 .set_rate = clk_plldiv_set_rate,
H A Dat91_h32mx.c52 .set_rate = clk_sama5d4_h32mx_set_rate,
H A Dat91_usb.c82 .set_rate = at91sam9x5_clk_usb_set_rate,
H A Dclk-sam9x60-pll.c272 .set_rate = sam9x60_frac_pll_set_rate_chg,
397 .set_rate = sam9x60_div_pll_set_rate,
404 .set_rate = sam9x60_div_pll_set_rate_chg,
H A Dat91_programmable.c130 .set_rate = clk_programmable_set_rate,
H A Dat91_peripheral.c145 .set_rate = clk_sam9x5_peripheral_set_rate,
H A Dat91_generated.c126 .set_rate = clk_generated_set_rate,
H A Dat91_master.c256 .set_rate = clk_sama7g5_master_set_rate,
H A Dat91_pll.c252 .set_rate = clk_pll_set_rate,
/optee_os/core/include/drivers/
H A Dclk.h84 TEE_Result (*set_rate)(struct clk *clk, unsigned long rate, member
/optee_os/core/drivers/clk/
H A Dclk.c228 if (clk->ops->set_rate) { in clk_set_rate_no_lock()
235 res = clk->ops->set_rate(clk, rate, parent_rate); in clk_set_rate_no_lock()
H A Dclk-stm32-core.c433 .set_rate = clk_stm32_divider_set_rate,
501 .set_rate = clk_stm32_composite_set_rate,
H A Dclk-stm32mp13.c1810 .set_rate = clk_stm32_composite_set_rate,
1885 .set_rate = clk_stm32_pll1_set_rate,
1906 .set_rate = clk_stm32_composite_set_rate,
1913 .set_rate = clk_stm32_composite_set_rate,
H A Dclk-stm32mp25.c2015 .set_rate = clk_stm32_msi_set_rate,
2027 .set_rate = clk_stm32_hse_div_set_rate,
2147 .set_rate = clk_stm32_pll1_set_rate,
2482 .set_rate = clk_stm32_flexgen_set_rate,
H A Dclk-stm32mp21.c2030 .set_rate = clk_stm32_hse_div_set_rate,
2154 .set_rate = clk_stm32_pll1_set_rate,
2461 .set_rate = clk_stm32_flexgen_set_rate,