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Searched refs:timings (Results 1 – 25 of 617) sorted by relevance

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/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c108 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, in ddrmc_ctrl_init_ddr3() argument
118 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
119 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
122 writel(DDRMC_CR12_WRLAT(timings->wrlat) | in ddrmc_ctrl_init_ddr3()
123 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
124 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | in ddrmc_ctrl_init_ddr3()
125 DDRMC_CR13_TCCD(timings->tccd) | in ddrmc_ctrl_init_ddr3()
126 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval), in ddrmc_ctrl_init_ddr3()
128 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
[all …]
/OK3568_Linux_fs/u-boot/board/overo/
H A Dspl.c25 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
27 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
30 timings->mcfg = MICRON_V_MCFG_165(256 << 20); in get_board_mem_timings()
31 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
32 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
33 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
37 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
38 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
39 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
40 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
[all …]
/OK3568_Linux_fs/u-boot/board/isee/igep00x0/
H A Dspl.c16 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
20 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
24 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
25 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
26 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
29 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
30 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
31 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
37 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
41 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); in get_board_mem_timings()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_wp.c145 struct omap_video_timings *timings) in hdmi_wp_video_config_interface() argument
151 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
152 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
157 r = FLD_MOD(r, timings->interlace, 3, 3); in hdmi_wp_video_config_interface()
163 struct omap_video_timings *timings) in hdmi_wp_video_config_timing() argument
170 timing_h |= FLD_VAL(timings->hbp, 31, 20); in hdmi_wp_video_config_timing()
171 timing_h |= FLD_VAL(timings->hfp, 19, 8); in hdmi_wp_video_config_timing()
172 timing_h |= FLD_VAL(timings->hsw, 7, 0); in hdmi_wp_video_config_timing()
175 timing_v |= FLD_VAL(timings->vbp, 31, 20); in hdmi_wp_video_config_timing()
176 timing_v |= FLD_VAL(timings->vfp, 19, 8); in hdmi_wp_video_config_timing()
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H A Dhdmi5_core.c286 video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level; in hdmi_core_init()
287 video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res; in hdmi_core_init()
288 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; in hdmi_core_init()
289 video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp; in hdmi_core_init()
290 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; in hdmi_core_init()
291 video_cfg->hblank = cfg->timings.hfp + in hdmi_core_init()
292 cfg->timings.hbp + cfg->timings.hsw - 1; in hdmi_core_init()
293 video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level; in hdmi_core_init()
294 video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res; in hdmi_core_init()
295 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; in hdmi_core_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/core/
H A Dfbmon.c1148 static void fb_timings_vfreq(struct __fb_timings *timings) in fb_timings_vfreq() argument
1150 timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive); in fb_timings_vfreq()
1151 timings->vblank = fb_get_vblank(timings->hfreq); in fb_timings_vfreq()
1152 timings->vtotal = timings->vactive + timings->vblank; in fb_timings_vfreq()
1153 timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq, in fb_timings_vfreq()
1154 timings->hactive); in fb_timings_vfreq()
1155 timings->htotal = timings->hactive + timings->hblank; in fb_timings_vfreq()
1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1159 static void fb_timings_hfreq(struct __fb_timings *timings) in fb_timings_hfreq() argument
1161 timings->vblank = fb_get_vblank(timings->hfreq); in fb_timings_hfreq()
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/OK3568_Linux_fs/u-boot/board/ti/beagle/
H A Dbeagle.c147 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
158 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
163 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); in get_board_mem_timings()
164 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
165 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
170 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
171 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
172 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
173 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
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/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dnand_timings.c26 .timings.mode = 0,
27 .timings.sdr = {
71 .timings.mode = 1,
72 .timings.sdr = {
116 .timings.mode = 2,
117 .timings.sdr = {
161 .timings.mode = 3,
162 .timings.sdr = {
206 .timings.mode = 4,
207 .timings.sdr = {
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/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c103 struct board_sdrc_timings *timings) in write_sdrc_timings() argument
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
107 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
108 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
109 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
114 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
133 struct board_sdrc_timings timings; in do_sdrc_init() local
139 timings.sharing = SDRC_SHARING; in do_sdrc_init()
152 get_board_mem_timings(&timings); in do_sdrc_init()
162 writel(timings.sharing, &sdrc_base->sharing); in do_sdrc_init()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c48 struct v4l2_dv_timings timings; member
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
102 fmt->width = hdmi->timings.bt.width; in adv748x_hdmi_fill_format()
103 fmt->height = hdmi->timings.bt.height; in adv748x_hdmi_fill_format()
109 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) in adv748x_fill_optional_dv_timings() argument
111 v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, in adv748x_fill_optional_dv_timings()
172 const struct v4l2_dv_timings *timings) in adv748x_hdmi_set_video_timings() argument
179 if (!v4l2_match_dv_timings(timings, &stds[i].timings, 250000, in adv748x_hdmi_set_video_timings()
218 struct v4l2_dv_timings *timings) in adv748x_hdmi_s_dv_timings() argument
224 if (!timings) in adv748x_hdmi_s_dv_timings()
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/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra210-emc-table.c16 struct tegra210_emc_timing *timings; in tegra210_emc_table_device_init() local
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
20 if (!timings) { in tegra210_emc_table_device_init()
28 if (timings[i].revision == 0) in tegra210_emc_table_device_init()
44 memunmap(timings); in tegra210_emc_table_device_init()
48 emc->derated = timings; in tegra210_emc_table_device_init()
51 emc->nominal = timings; in tegra210_emc_table_device_init()
56 rmem->priv = timings; in tegra210_emc_table_device_init()
64 struct tegra210_emc_timing *timings = rmem->priv; in tegra210_emc_table_device_release() local
67 if ((emc->nominal && timings != emc->nominal) && in tegra210_emc_table_device_release()
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/OK3568_Linux_fs/kernel/drivers/memory/
H A Dpl353-smc.c118 void pl353_smc_set_cycles(u32 timings[]) in pl353_smc_set_cycles() argument
125 timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK; in pl353_smc_set_cycles()
126 timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) << in pl353_smc_set_cycles()
128 timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) << in pl353_smc_set_cycles()
130 timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) << in pl353_smc_set_cycles()
132 timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) << in pl353_smc_set_cycles()
134 timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) << in pl353_smc_set_cycles()
136 timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) << in pl353_smc_set_cycles()
138 timings[0] |= timings[1] | timings[2] | timings[3] | in pl353_smc_set_cycles()
139 timings[4] | timings[5] | timings[6]; in pl353_smc_set_cycles()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/displays/
H A Dencoder-tfp410.c24 struct omap_video_timings timings; member
81 in->ops.dpi->set_timings(in, &ddata->timings); in tfp410_enable()
113 static void tfp410_fix_timings(struct omap_video_timings *timings) in tfp410_fix_timings() argument
115 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
116 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
117 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH; in tfp410_fix_timings()
121 struct omap_video_timings *timings) in tfp410_set_timings() argument
126 tfp410_fix_timings(timings); in tfp410_set_timings()
128 ddata->timings = *timings; in tfp410_set_timings()
129 dssdev->panel.timings = *timings; in tfp410_set_timings()
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H A Dconnector-analog-tv.c23 struct omap_video_timings timings; member
91 in->ops.atv->set_timings(in, &ddata->timings); in tvc_enable()
125 struct omap_video_timings *timings) in tvc_set_timings() argument
130 ddata->timings = *timings; in tvc_set_timings()
131 dssdev->panel.timings = *timings; in tvc_set_timings()
133 in->ops.atv->set_timings(in, timings); in tvc_set_timings()
137 struct omap_video_timings *timings) in tvc_get_timings() argument
141 *timings = ddata->timings; in tvc_get_timings()
145 struct omap_video_timings *timings) in tvc_check_timings() argument
150 return in->ops.atv->check_timings(in, timings); in tvc_check_timings()
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/OK3568_Linux_fs/kernel/drivers/media/rc/
H A Drc-ir-raw.c319 const struct ir_raw_timings_manchester *timings, in ir_raw_gen_manchester() argument
328 if (timings->leader_pulse) { in ir_raw_gen_manchester()
331 init_ir_raw_event_duration((*ev), 1, timings->leader_pulse); in ir_raw_gen_manchester()
332 if (timings->leader_space) { in ir_raw_gen_manchester()
336 timings->leader_space); in ir_raw_gen_manchester()
346 if (timings->invert) in ir_raw_gen_manchester()
349 (*ev)->duration += timings->clock; in ir_raw_gen_manchester()
354 timings->clock); in ir_raw_gen_manchester()
360 timings->clock); in ir_raw_gen_manchester()
364 if (timings->trailer_space) { in ir_raw_gen_manchester()
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/OK3568_Linux_fs/kernel/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst23 GPMC has certain timings that has to be programmed for proper
25 timings. To have peripheral work with gpmc, peripheral timings has to
28 dependency for certain gpmc timings on gpmc clock frequency. Hence a
31 Generic routine provides a generic method to calculate gpmc timings
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
49 on understanding of gpmc timings, peripheral timings, available
54 gpmc timing dependency on peripheral timings:
172 Many of gpmc timings are dependent on other gpmc timings (a few
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/OK3568_Linux_fs/kernel/drivers/ide/
H A Dcs5536.c137 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_set_pio_mode() local
145 timings &= (IDE_DRV_MASK << 8); in cs5536_set_pio_mode()
146 timings |= drv_timings[pio]; in cs5536_set_pio_mode()
147 ide_set_drivedata(drive, (void *)timings); in cs5536_set_pio_mode()
180 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_set_dma_mode() local
191 timings &= IDE_DRV_MASK; in cs5536_set_dma_mode()
192 timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8; in cs5536_set_dma_mode()
193 ide_set_drivedata(drive, (void *)timings); in cs5536_set_dma_mode()
201 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_dma_start() local
204 (timings >> 8) != (timings & IDE_DRV_MASK)) in cs5536_dma_start()
[all …]
H A Dcs5530.c39 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132) argument
106 unsigned int reg, timings = 0; in cs5530_set_dma_mode() local
109 case XFER_UDMA_0: timings = 0x00921250; break; in cs5530_set_dma_mode()
110 case XFER_UDMA_1: timings = 0x00911140; break; in cs5530_set_dma_mode()
111 case XFER_UDMA_2: timings = 0x00911030; break; in cs5530_set_dma_mode()
112 case XFER_MW_DMA_0: timings = 0x00077771; break; in cs5530_set_dma_mode()
113 case XFER_MW_DMA_1: timings = 0x00012121; break; in cs5530_set_dma_mode()
114 case XFER_MW_DMA_2: timings = 0x00002020; break; in cs5530_set_dma_mode()
118 timings |= reg & 0x80000000; /* preserve PIO format bit */ in cs5530_set_dma_mode()
120 outl(timings, basereg + 4); /* write drive0 config register */ in cs5530_set_dma_mode()
[all …]
/OK3568_Linux_fs/u-boot/board/corscience/tricorder/
H A Dtricorder.c164 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
172 timings->mcfg = MCFG((256 << 20), 14); in get_board_mem_timings()
182 timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, in get_board_mem_timings()
192 timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, in get_board_mem_timings()
195 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
196 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
199 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
200 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
201 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
202 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
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/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
117 geometry 640 480 640 480 32 timings 19081 104 40 31 1 64 3 endmode
138 geometry 720 480 720 480 32 timings 37202 88 16 14 1 72 3 endmode
159 geometry 800 480 800 480 32 timings 33805 96 24 10 3 72 7 endmode
180 geometry 720 576 720 576 32 timings 30611 96 24 17 1 72 3 endmode
202 timings 25000 88 40 23 1 128 4 hsync high vsync high endmode
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/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Dnand_timings.c19 .timings.sdr = {
61 .timings.sdr = {
103 .timings.sdr = {
145 .timings.sdr = {
187 .timings.sdr = {
229 .timings.sdr = {
280 return &onfi_sdr_timings[mode].timings.sdr; in onfi_async_timing_mode_to_sdr_timings()
310 struct nand_sdr_timings *timings = &iface->timings.sdr; in onfi_init_data_interface() local
313 timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); in onfi_init_data_interface()
314 timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers); in onfi_init_data_interface()
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/OK3568_Linux_fs/kernel/drivers/media/spi/
H A Dgs1662.c229 static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) in gs_status_format() argument
236 *timings = reg_fmt[i].format; in gs_status_format()
244 static u16 get_register_timings(struct v4l2_dv_timings *timings) in get_register_timings() argument
249 if (v4l2_match_dv_timings(timings, &reg_fmt[i].format, 0, in get_register_timings()
263 struct v4l2_dv_timings *timings) in gs_s_dv_timings() argument
268 reg_value = get_register_timings(timings); in gs_s_dv_timings()
272 gs->current_timings = *timings; in gs_s_dv_timings()
277 struct v4l2_dv_timings *timings) in gs_g_dv_timings() argument
281 *timings = gs->current_timings; in gs_g_dv_timings()
286 struct v4l2_dv_timings *timings) in gs_query_dv_timings() argument
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/OK3568_Linux_fs/kernel/Documentation/userspace-api/media/v4l/
H A Ddv-timings.rst3 .. _dv-timings:
10 and the corresponding video timings. Today there are many more different
13 extend the API to select the video timings for these interfaces. Since
16 set/get video timings at the input and output.
18 These ioctls deal with the detailed digital video timings that define
21 widths etc. The ``linux/v4l2-dv-timings.h`` header can be used to get
22 the timings of the formats in the :ref:`cea861` and :ref:`vesadmt`
25 To enumerate and query the attributes of the DV timings supported by a
29 DV timings for the device applications use the
31 current DV timings they use the
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H A Dvidioc-enum-dv-timings.rst13 VIDIOC_ENUM_DV_TIMINGS - VIDIOC_SUBDEV_ENUM_DV_TIMINGS - Enumerate supported Digital Video timings
38 While some DV receivers or transmitters support a wide range of timings,
39 others support only a limited number of timings. With this ioctl
40 applications can enumerate a list of known supported timings. Call
42 also supports other standards or even custom timings that are not in
45 To query the available timings, applications initialize the ``index``
51 DV timings, applications shall begin at index zero, incrementing by one
56 Drivers may enumerate a different set of DV timings after
59 When implemented by the driver DV timings of subdevices can be queried
61 subdevice node. The DV timings are specific to inputs (for DV receivers)
[all …]
/OK3568_Linux_fs/u-boot/board/quipos/cairo/
H A Dcairo.c70 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
72 timings->sharing = SAMSUNG_SHARING; in get_board_mem_timings()
73 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); in get_board_mem_timings()
74 timings->ctrla = SAMSUNG_V_ACTIMA_165; in get_board_mem_timings()
75 timings->ctrlb = SAMSUNG_V_ACTIMB_165; in get_board_mem_timings()
76 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
77 timings->mr = SAMSUNG_V_MR_165; in get_board_mem_timings()

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