1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun #include <asm/io.h> 5*4882a593Smuzhiyun #include <asm/arch/mem.h> 6*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 7*4882a593Smuzhiyun #include <jffs2/load_kernel.h> 8*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 9*4882a593Smuzhiyun #include "igep00x0.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Routine: get_board_mem_timings 13*4882a593Smuzhiyun * Description: If we use SPL then there is no x-loader nor config header 14*4882a593Smuzhiyun * so we have to setup the DDR timings ourself on both banks. 15*4882a593Smuzhiyun */ get_board_mem_timings(struct board_sdrc_timings * timings)16*4882a593Smuzhiyunvoid get_board_mem_timings(struct board_sdrc_timings *timings) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun int mfr, id, err = identify_nand_chip(&mfr, &id); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun timings->mr = MICRON_V_MR_165; 21*4882a593Smuzhiyun if (!err) { 22*4882a593Smuzhiyun switch (mfr) { 23*4882a593Smuzhiyun case NAND_MFR_HYNIX: 24*4882a593Smuzhiyun timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 25*4882a593Smuzhiyun timings->ctrla = HYNIX_V_ACTIMA_200; 26*4882a593Smuzhiyun timings->ctrlb = HYNIX_V_ACTIMB_200; 27*4882a593Smuzhiyun break; 28*4882a593Smuzhiyun case NAND_MFR_MICRON: 29*4882a593Smuzhiyun timings->mcfg = MICRON_V_MCFG_200(256 << 20); 30*4882a593Smuzhiyun timings->ctrla = MICRON_V_ACTIMA_200; 31*4882a593Smuzhiyun timings->ctrlb = MICRON_V_ACTIMB_200; 32*4882a593Smuzhiyun break; 33*4882a593Smuzhiyun default: 34*4882a593Smuzhiyun /* Should not happen... */ 35*4882a593Smuzhiyun break; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 38*4882a593Smuzhiyun gpmc_cs0_flash = MTD_DEV_TYPE_NAND; 39*4882a593Smuzhiyun } else { 40*4882a593Smuzhiyun if (get_cpu_family() == CPU_OMAP34XX) { 41*4882a593Smuzhiyun timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 42*4882a593Smuzhiyun timings->ctrla = NUMONYX_V_ACTIMA_165; 43*4882a593Smuzhiyun timings->ctrlb = NUMONYX_V_ACTIMB_165; 44*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 45*4882a593Smuzhiyun } else { 46*4882a593Smuzhiyun timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 47*4882a593Smuzhiyun timings->ctrla = NUMONYX_V_ACTIMA_200; 48*4882a593Smuzhiyun timings->ctrlb = NUMONYX_V_ACTIMB_200; 49*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT spl_start_uboot(void)56*4882a593Smuzhiyunint spl_start_uboot(void) 57*4882a593Smuzhiyun { 58*4882a593Smuzhiyun /* break into full u-boot on 'c' */ 59*4882a593Smuzhiyun if (serial_tstc() && serial_getc() == 'c') 60*4882a593Smuzhiyun return 1; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun return 0; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun #endif 65