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Searched refs:slcr (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
99 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
101 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
103 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/OK3568_Linux_fs/kernel/drivers/fpga/
H A Dzynq-fpga.c127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
573 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
575 return PTR_ERR(priv->slcr); in zynq_fpga_probe()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi258 slcr: slcr@f8000000 { label
262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
288 syscon = <&slcr>;
294 syscon = <&slcr>;
323 syscon = <&slcr>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dzynq-7000.dtsi275 slcr: slcr@f8000000 { label
278 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
303 syscon = <&slcr>;
309 syscon = <&slcr>;
338 syscon = <&slcr>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt10 - syscon: <&slcr>
21 syscon = <&slcr>;
/OK3568_Linux_fs/kernel/drivers/clk/zynq/
H A Dclkc.c584 struct device_node *slcr; in zynq_clock_init() local
598 slcr = of_get_parent(np); in zynq_clock_init()
600 if (slcr->data) { in zynq_clock_init()
601 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
604 of_node_put(slcr); in zynq_clock_init()
610 of_node_put(slcr); in zynq_clock_init()
/OK3568_Linux_fs/kernel/arch/arm/mach-zynq/
H A DMakefile7 obj-y := common.o slcr.o pm.o
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/zynqmp/
H A DMakefile11 obj-y += slcr.o
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.zynq38 Zynq has a facility to read the bootmode from the slcr bootmode register
44 board_late_init() will read the bootmode values using slcr bootmode register
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A DMakefile14 obj-y += slcr.o
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.txt18 syscon = <&slcr>;
H A Dfpga-region.txt362 syscon = <&slcr>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/xilinx/
H A Dxlnx,vcu.txt16 1. vcu slcr
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynq-pinctrl.txt81 syscon = <&slcr>;
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1452 MLXSW_REG_ZERO(slcr, payload); in mlxsw_reg_slcr_pack()
11127 MLXSW_REG(slcr),
H A Dspectrum.c2439 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()