1*4882a593SmuzhiyunXilinx Zynq FPGA Manager 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should contain "xlnx,zynq-devcfg-1.0" 5*4882a593Smuzhiyun- reg: base address and size for memory mapped io 6*4882a593Smuzhiyun- interrupts: interrupt for the FPGA manager device 7*4882a593Smuzhiyun- clocks: phandle for clocks required operation 8*4882a593Smuzhiyun- clock-names: name for the clock, should be "ref_clk" 9*4882a593Smuzhiyun- syscon: phandle for access to SLCR registers 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunExample: 12*4882a593Smuzhiyun devcfg: devcfg@f8007000 { 13*4882a593Smuzhiyun compatible = "xlnx,zynq-devcfg-1.0"; 14*4882a593Smuzhiyun reg = <0xf8007000 0x100>; 15*4882a593Smuzhiyun interrupts = <0 8 4>; 16*4882a593Smuzhiyun clocks = <&clkc 12>; 17*4882a593Smuzhiyun clock-names = "ref_clk"; 18*4882a593Smuzhiyun syscon = <&slcr>; 19*4882a593Smuzhiyun }; 20